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[PATCH] x86: add support for AVX-512 VPCMP*{B,W} pseudo-ops
- From: "Jan Beulich" <JBeulich at suse dot com>
- To: <binutils at sourceware dot org>
- Cc: "H.J. Lu" <hjl dot tools at gmail dot com>
- Date: Mon, 13 Nov 2017 05:14:19 -0700
- Subject: [PATCH] x86: add support for AVX-512 VPCMP*{B,W} pseudo-ops
- Authentication-results: sourceware.org; auth=none
... matching up with VPCMP*{D,Q}.
gas/
2017-11-13 Jan Beulich <jbeulich@suse.com>
* testsuite/gas/i386/avx512bw.s: Add vpcmp* pseudo tests.
* testsuite/gas/i386/avx512bw_vl.s: Likewise.
* testsuite/gas/i386/avx512bw.d, testsuite/gas/i386/avx512bw-intel.d,
testsuite/gas/i386/avx512bw_vl.d,
testsuite/gas/i386/avx512bw_vl-intel.d: Adjust expectations.
opcodes/
2017-11-13 Jan Beulich <jbeulich@suse.com>
* i386-dis-evex.h (evex_table[EVEX_W_0F3A3E_P_2]): Use VPCMP.
(evex_table[EVEX_W_0F3A3F_P_2]): Likewise.
* i386-opc.tbl (vpcmpeqb, vpcmpgtb, vpcmpeqw, vpcmpgtw, vpcmpuw,
vpcmpw): Move up.
(vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb, vpcmpnleb, vpcmpnltb,
vpcmpequb, vpcmpleub, vpcmpltub, vpcmpnequb, vpcmpnleub,
vpcmpnltub, vpcmpeqw, vpcmplew, vpcmpltw, vpcmpneqw, vpcmpnlew,
vpcmpnltw, vpcmpequw, vpcmpleuw, vpcmpltuw, vpcmpnequw, vpcmpnleuw,
vpcmpnltuw): New.
* i386-tbl.h: Re-generate.
--- 2017-11-10/gas/testsuite/gas/i386/avx512bw-intel.d
+++ 2017-11-10/gas/testsuite/gas/i386/avx512bw-intel.d
@@ -777,6 +777,12 @@ Disassembly of section \.text:
[ ]*[a-f0-9]+:[ ]*62 f3 4d 48 3f aa 00 20 00 00 7b[ ]*vpcmpb k5,zmm6,ZMMWORD PTR \[edx\+0x2000\],0x7b
[ ]*[a-f0-9]+:[ ]*62 f3 4d 48 3f 6a 80 7b[ ]*vpcmpb k5,zmm6,ZMMWORD PTR \[edx-0x2000\],0x7b
[ ]*[a-f0-9]+:[ ]*62 f3 4d 48 3f aa c0 df ff ff 7b[ ]*vpcmpb k5,zmm6,ZMMWORD PTR \[edx-0x2040\],0x7b
+[ ]*[a-f0-9]+:[ ]*62 f3 4d 48 3f ed 00[ ]*vpcmpeqb k5,zmm6,zmm5
+[ ]*[a-f0-9]+:[ ]*62 f3 4d 48 3f ed 02[ ]*vpcmpleb k5,zmm6,zmm5
+[ ]*[a-f0-9]+:[ ]*62 f3 4d 48 3f ed 01[ ]*vpcmpltb k5,zmm6,zmm5
+[ ]*[a-f0-9]+:[ ]*62 f3 4d 48 3f ed 04[ ]*vpcmpneqb k5,zmm6,zmm5
+[ ]*[a-f0-9]+:[ ]*62 f3 4d 48 3f ed 06[ ]*vpcmpnleb k5,zmm6,zmm5
+[ ]*[a-f0-9]+:[ ]*62 f3 4d 48 3f ed 05[ ]*vpcmpnltb k5,zmm6,zmm5
[ ]*[a-f0-9]+:[ ]*62 f3 cd 48 3f ed ab[ ]*vpcmpw k5,zmm6,zmm5,0xab
[ ]*[a-f0-9]+:[ ]*62 f3 cd 4f 3f ed ab[ ]*vpcmpw k5\{k7\},zmm6,zmm5,0xab
[ ]*[a-f0-9]+:[ ]*62 f3 cd 48 3f ed 7b[ ]*vpcmpw k5,zmm6,zmm5,0x7b
@@ -786,6 +792,12 @@ Disassembly of section \.text:
[ ]*[a-f0-9]+:[ ]*62 f3 cd 48 3f aa 00 20 00 00 7b[ ]*vpcmpw k5,zmm6,ZMMWORD PTR \[edx\+0x2000\],0x7b
[ ]*[a-f0-9]+:[ ]*62 f3 cd 48 3f 6a 80 7b[ ]*vpcmpw k5,zmm6,ZMMWORD PTR \[edx-0x2000\],0x7b
[ ]*[a-f0-9]+:[ ]*62 f3 cd 48 3f aa c0 df ff ff 7b[ ]*vpcmpw k5,zmm6,ZMMWORD PTR \[edx-0x2040\],0x7b
+[ ]*[a-f0-9]+:[ ]*62 f3 cd 48 3f ed 00[ ]*vpcmpeqw k5,zmm6,zmm5
+[ ]*[a-f0-9]+:[ ]*62 f3 cd 48 3f ed 02[ ]*vpcmplew k5,zmm6,zmm5
+[ ]*[a-f0-9]+:[ ]*62 f3 cd 48 3f ed 01[ ]*vpcmpltw k5,zmm6,zmm5
+[ ]*[a-f0-9]+:[ ]*62 f3 cd 48 3f ed 04[ ]*vpcmpneqw k5,zmm6,zmm5
+[ ]*[a-f0-9]+:[ ]*62 f3 cd 48 3f ed 06[ ]*vpcmpnlew k5,zmm6,zmm5
+[ ]*[a-f0-9]+:[ ]*62 f3 cd 48 3f ed 05[ ]*vpcmpnltw k5,zmm6,zmm5
[ ]*[a-f0-9]+:[ ]*62 f3 4d 48 3e ed ab[ ]*vpcmpub k5,zmm6,zmm5,0xab
[ ]*[a-f0-9]+:[ ]*62 f3 4d 4f 3e ed ab[ ]*vpcmpub k5\{k7\},zmm6,zmm5,0xab
[ ]*[a-f0-9]+:[ ]*62 f3 4d 48 3e ed 7b[ ]*vpcmpub k5,zmm6,zmm5,0x7b
@@ -795,6 +807,12 @@ Disassembly of section \.text:
[ ]*[a-f0-9]+:[ ]*62 f3 4d 48 3e aa 00 20 00 00 7b[ ]*vpcmpub k5,zmm6,ZMMWORD PTR \[edx\+0x2000\],0x7b
[ ]*[a-f0-9]+:[ ]*62 f3 4d 48 3e 6a 80 7b[ ]*vpcmpub k5,zmm6,ZMMWORD PTR \[edx-0x2000\],0x7b
[ ]*[a-f0-9]+:[ ]*62 f3 4d 48 3e aa c0 df ff ff 7b[ ]*vpcmpub k5,zmm6,ZMMWORD PTR \[edx-0x2040\],0x7b
+[ ]*[a-f0-9]+:[ ]*62 f3 4d 48 3e ed 00[ ]*vpcmpequb k5,zmm6,zmm5
+[ ]*[a-f0-9]+:[ ]*62 f3 4d 48 3e ed 02[ ]*vpcmpleub k5,zmm6,zmm5
+[ ]*[a-f0-9]+:[ ]*62 f3 4d 48 3e ed 01[ ]*vpcmpltub k5,zmm6,zmm5
+[ ]*[a-f0-9]+:[ ]*62 f3 4d 48 3e ed 04[ ]*vpcmpnequb k5,zmm6,zmm5
+[ ]*[a-f0-9]+:[ ]*62 f3 4d 48 3e ed 06[ ]*vpcmpnleub k5,zmm6,zmm5
+[ ]*[a-f0-9]+:[ ]*62 f3 4d 48 3e ed 05[ ]*vpcmpnltub k5,zmm6,zmm5
[ ]*[a-f0-9]+:[ ]*62 f3 cd 48 3e ed ab[ ]*vpcmpuw k5,zmm6,zmm5,0xab
[ ]*[a-f0-9]+:[ ]*62 f3 cd 4f 3e ed ab[ ]*vpcmpuw k5\{k7\},zmm6,zmm5,0xab
[ ]*[a-f0-9]+:[ ]*62 f3 cd 48 3e ed 7b[ ]*vpcmpuw k5,zmm6,zmm5,0x7b
@@ -804,6 +822,12 @@ Disassembly of section \.text:
[ ]*[a-f0-9]+:[ ]*62 f3 cd 48 3e aa 00 20 00 00 7b[ ]*vpcmpuw k5,zmm6,ZMMWORD PTR \[edx\+0x2000\],0x7b
[ ]*[a-f0-9]+:[ ]*62 f3 cd 48 3e 6a 80 7b[ ]*vpcmpuw k5,zmm6,ZMMWORD PTR \[edx-0x2000\],0x7b
[ ]*[a-f0-9]+:[ ]*62 f3 cd 48 3e aa c0 df ff ff 7b[ ]*vpcmpuw k5,zmm6,ZMMWORD PTR \[edx-0x2040\],0x7b
+[ ]*[a-f0-9]+:[ ]*62 f3 cd 48 3e ed 00[ ]*vpcmpequw k5,zmm6,zmm5
+[ ]*[a-f0-9]+:[ ]*62 f3 cd 48 3e ed 02[ ]*vpcmpleuw k5,zmm6,zmm5
+[ ]*[a-f0-9]+:[ ]*62 f3 cd 48 3e ed 01[ ]*vpcmpltuw k5,zmm6,zmm5
+[ ]*[a-f0-9]+:[ ]*62 f3 cd 48 3e ed 04[ ]*vpcmpnequw k5,zmm6,zmm5
+[ ]*[a-f0-9]+:[ ]*62 f3 cd 48 3e ed 06[ ]*vpcmpnleuw k5,zmm6,zmm5
+[ ]*[a-f0-9]+:[ ]*62 f3 cd 48 3e ed 05[ ]*vpcmpnltuw k5,zmm6,zmm5
[ ]*[a-f0-9]+:[ ]*62 f2 7d 48 1c f5[ ]*vpabsb zmm6,zmm5
[ ]*[a-f0-9]+:[ ]*62 f2 7d 4f 1c f5[ ]*vpabsb zmm6\{k7\},zmm5
[ ]*[a-f0-9]+:[ ]*62 f2 7d cf 1c f5[ ]*vpabsb zmm6\{k7\}\{z\},zmm5
--- 2017-11-10/gas/testsuite/gas/i386/avx512bw.d
+++ 2017-11-10/gas/testsuite/gas/i386/avx512bw.d
@@ -777,6 +777,12 @@ Disassembly of section \.text:
[ ]*[a-f0-9]+:[ ]*62 f3 4d 48 3f aa 00 20 00 00 7b[ ]*vpcmpb \$0x7b,0x2000\(%edx\),%zmm6,%k5
[ ]*[a-f0-9]+:[ ]*62 f3 4d 48 3f 6a 80 7b[ ]*vpcmpb \$0x7b,-0x2000\(%edx\),%zmm6,%k5
[ ]*[a-f0-9]+:[ ]*62 f3 4d 48 3f aa c0 df ff ff 7b[ ]*vpcmpb \$0x7b,-0x2040\(%edx\),%zmm6,%k5
+[ ]*[a-f0-9]+:[ ]*62 f3 4d 48 3f ed 00[ ]*vpcmpeqb %zmm5,%zmm6,%k5
+[ ]*[a-f0-9]+:[ ]*62 f3 4d 48 3f ed 02[ ]*vpcmpleb %zmm5,%zmm6,%k5
+[ ]*[a-f0-9]+:[ ]*62 f3 4d 48 3f ed 01[ ]*vpcmpltb %zmm5,%zmm6,%k5
+[ ]*[a-f0-9]+:[ ]*62 f3 4d 48 3f ed 04[ ]*vpcmpneqb %zmm5,%zmm6,%k5
+[ ]*[a-f0-9]+:[ ]*62 f3 4d 48 3f ed 06[ ]*vpcmpnleb %zmm5,%zmm6,%k5
+[ ]*[a-f0-9]+:[ ]*62 f3 4d 48 3f ed 05[ ]*vpcmpnltb %zmm5,%zmm6,%k5
[ ]*[a-f0-9]+:[ ]*62 f3 cd 48 3f ed ab[ ]*vpcmpw \$0xab,%zmm5,%zmm6,%k5
[ ]*[a-f0-9]+:[ ]*62 f3 cd 4f 3f ed ab[ ]*vpcmpw \$0xab,%zmm5,%zmm6,%k5\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f3 cd 48 3f ed 7b[ ]*vpcmpw \$0x7b,%zmm5,%zmm6,%k5
@@ -786,6 +792,12 @@ Disassembly of section \.text:
[ ]*[a-f0-9]+:[ ]*62 f3 cd 48 3f aa 00 20 00 00 7b[ ]*vpcmpw \$0x7b,0x2000\(%edx\),%zmm6,%k5
[ ]*[a-f0-9]+:[ ]*62 f3 cd 48 3f 6a 80 7b[ ]*vpcmpw \$0x7b,-0x2000\(%edx\),%zmm6,%k5
[ ]*[a-f0-9]+:[ ]*62 f3 cd 48 3f aa c0 df ff ff 7b[ ]*vpcmpw \$0x7b,-0x2040\(%edx\),%zmm6,%k5
+[ ]*[a-f0-9]+:[ ]*62 f3 cd 48 3f ed 00[ ]*vpcmpeqw %zmm5,%zmm6,%k5
+[ ]*[a-f0-9]+:[ ]*62 f3 cd 48 3f ed 02[ ]*vpcmplew %zmm5,%zmm6,%k5
+[ ]*[a-f0-9]+:[ ]*62 f3 cd 48 3f ed 01[ ]*vpcmpltw %zmm5,%zmm6,%k5
+[ ]*[a-f0-9]+:[ ]*62 f3 cd 48 3f ed 04[ ]*vpcmpneqw %zmm5,%zmm6,%k5
+[ ]*[a-f0-9]+:[ ]*62 f3 cd 48 3f ed 06[ ]*vpcmpnlew %zmm5,%zmm6,%k5
+[ ]*[a-f0-9]+:[ ]*62 f3 cd 48 3f ed 05[ ]*vpcmpnltw %zmm5,%zmm6,%k5
[ ]*[a-f0-9]+:[ ]*62 f3 4d 48 3e ed ab[ ]*vpcmpub \$0xab,%zmm5,%zmm6,%k5
[ ]*[a-f0-9]+:[ ]*62 f3 4d 4f 3e ed ab[ ]*vpcmpub \$0xab,%zmm5,%zmm6,%k5\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f3 4d 48 3e ed 7b[ ]*vpcmpub \$0x7b,%zmm5,%zmm6,%k5
@@ -795,6 +807,12 @@ Disassembly of section \.text:
[ ]*[a-f0-9]+:[ ]*62 f3 4d 48 3e aa 00 20 00 00 7b[ ]*vpcmpub \$0x7b,0x2000\(%edx\),%zmm6,%k5
[ ]*[a-f0-9]+:[ ]*62 f3 4d 48 3e 6a 80 7b[ ]*vpcmpub \$0x7b,-0x2000\(%edx\),%zmm6,%k5
[ ]*[a-f0-9]+:[ ]*62 f3 4d 48 3e aa c0 df ff ff 7b[ ]*vpcmpub \$0x7b,-0x2040\(%edx\),%zmm6,%k5
+[ ]*[a-f0-9]+:[ ]*62 f3 4d 48 3e ed 00[ ]*vpcmpequb %zmm5,%zmm6,%k5
+[ ]*[a-f0-9]+:[ ]*62 f3 4d 48 3e ed 02[ ]*vpcmpleub %zmm5,%zmm6,%k5
+[ ]*[a-f0-9]+:[ ]*62 f3 4d 48 3e ed 01[ ]*vpcmpltub %zmm5,%zmm6,%k5
+[ ]*[a-f0-9]+:[ ]*62 f3 4d 48 3e ed 04[ ]*vpcmpnequb %zmm5,%zmm6,%k5
+[ ]*[a-f0-9]+:[ ]*62 f3 4d 48 3e ed 06[ ]*vpcmpnleub %zmm5,%zmm6,%k5
+[ ]*[a-f0-9]+:[ ]*62 f3 4d 48 3e ed 05[ ]*vpcmpnltub %zmm5,%zmm6,%k5
[ ]*[a-f0-9]+:[ ]*62 f3 cd 48 3e ed ab[ ]*vpcmpuw \$0xab,%zmm5,%zmm6,%k5
[ ]*[a-f0-9]+:[ ]*62 f3 cd 4f 3e ed ab[ ]*vpcmpuw \$0xab,%zmm5,%zmm6,%k5\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f3 cd 48 3e ed 7b[ ]*vpcmpuw \$0x7b,%zmm5,%zmm6,%k5
@@ -804,6 +822,12 @@ Disassembly of section \.text:
[ ]*[a-f0-9]+:[ ]*62 f3 cd 48 3e aa 00 20 00 00 7b[ ]*vpcmpuw \$0x7b,0x2000\(%edx\),%zmm6,%k5
[ ]*[a-f0-9]+:[ ]*62 f3 cd 48 3e 6a 80 7b[ ]*vpcmpuw \$0x7b,-0x2000\(%edx\),%zmm6,%k5
[ ]*[a-f0-9]+:[ ]*62 f3 cd 48 3e aa c0 df ff ff 7b[ ]*vpcmpuw \$0x7b,-0x2040\(%edx\),%zmm6,%k5
+[ ]*[a-f0-9]+:[ ]*62 f3 cd 48 3e ed 00[ ]*vpcmpequw %zmm5,%zmm6,%k5
+[ ]*[a-f0-9]+:[ ]*62 f3 cd 48 3e ed 02[ ]*vpcmpleuw %zmm5,%zmm6,%k5
+[ ]*[a-f0-9]+:[ ]*62 f3 cd 48 3e ed 01[ ]*vpcmpltuw %zmm5,%zmm6,%k5
+[ ]*[a-f0-9]+:[ ]*62 f3 cd 48 3e ed 04[ ]*vpcmpnequw %zmm5,%zmm6,%k5
+[ ]*[a-f0-9]+:[ ]*62 f3 cd 48 3e ed 06[ ]*vpcmpnleuw %zmm5,%zmm6,%k5
+[ ]*[a-f0-9]+:[ ]*62 f3 cd 48 3e ed 05[ ]*vpcmpnltuw %zmm5,%zmm6,%k5
[ ]*[a-f0-9]+:[ ]*62 f2 7d 48 1c f5[ ]*vpabsb %zmm5,%zmm6
[ ]*[a-f0-9]+:[ ]*62 f2 7d 4f 1c f5[ ]*vpabsb %zmm5,%zmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 7d cf 1c f5[ ]*vpabsb %zmm5,%zmm6\{%k7\}\{z\}
--- 2017-11-10/gas/testsuite/gas/i386/avx512bw.s
+++ 2017-11-10/gas/testsuite/gas/i386/avx512bw.s
@@ -771,6 +771,12 @@ _start:
vpcmpb $123, 8192(%edx), %zmm6, %k5 # AVX512BW
vpcmpb $123, -8192(%edx), %zmm6, %k5 # AVX512BW Disp8
vpcmpb $123, -8256(%edx), %zmm6, %k5 # AVX512BW
+ vpcmpb $0, %zmm5, %zmm6, %k5 # AVX512BW
+ vpcmpleb %zmm5, %zmm6, %k5 # AVX512BW
+ vpcmpltb %zmm5, %zmm6, %k5 # AVX512BW
+ vpcmpneqb %zmm5, %zmm6, %k5 # AVX512BW
+ vpcmpnleb %zmm5, %zmm6, %k5 # AVX512BW
+ vpcmpnltb %zmm5, %zmm6, %k5 # AVX512BW
vpcmpw $0xab, %zmm5, %zmm6, %k5 # AVX512BW
vpcmpw $0xab, %zmm5, %zmm6, %k5{%k7} # AVX512BW
vpcmpw $123, %zmm5, %zmm6, %k5 # AVX512BW
@@ -780,6 +786,12 @@ _start:
vpcmpw $123, 8192(%edx), %zmm6, %k5 # AVX512BW
vpcmpw $123, -8192(%edx), %zmm6, %k5 # AVX512BW Disp8
vpcmpw $123, -8256(%edx), %zmm6, %k5 # AVX512BW
+ vpcmpw $0, %zmm5, %zmm6, %k5 # AVX512BW
+ vpcmplew %zmm5, %zmm6, %k5 # AVX512BW
+ vpcmpltw %zmm5, %zmm6, %k5 # AVX512BW
+ vpcmpneqw %zmm5, %zmm6, %k5 # AVX512BW
+ vpcmpnlew %zmm5, %zmm6, %k5 # AVX512BW
+ vpcmpnltw %zmm5, %zmm6, %k5 # AVX512BW
vpcmpub $0xab, %zmm5, %zmm6, %k5 # AVX512BW
vpcmpub $0xab, %zmm5, %zmm6, %k5{%k7} # AVX512BW
vpcmpub $123, %zmm5, %zmm6, %k5 # AVX512BW
@@ -789,6 +801,12 @@ _start:
vpcmpub $123, 8192(%edx), %zmm6, %k5 # AVX512BW
vpcmpub $123, -8192(%edx), %zmm6, %k5 # AVX512BW Disp8
vpcmpub $123, -8256(%edx), %zmm6, %k5 # AVX512BW
+ vpcmpequb %zmm5, %zmm6, %k5 # AVX512BW
+ vpcmpleub %zmm5, %zmm6, %k5 # AVX512BW
+ vpcmpltub %zmm5, %zmm6, %k5 # AVX512BW
+ vpcmpnequb %zmm5, %zmm6, %k5 # AVX512BW
+ vpcmpnleub %zmm5, %zmm6, %k5 # AVX512BW
+ vpcmpnltub %zmm5, %zmm6, %k5 # AVX512BW
vpcmpuw $0xab, %zmm5, %zmm6, %k5 # AVX512BW
vpcmpuw $0xab, %zmm5, %zmm6, %k5{%k7} # AVX512BW
vpcmpuw $123, %zmm5, %zmm6, %k5 # AVX512BW
@@ -798,6 +816,12 @@ _start:
vpcmpuw $123, 8192(%edx), %zmm6, %k5 # AVX512BW
vpcmpuw $123, -8192(%edx), %zmm6, %k5 # AVX512BW Disp8
vpcmpuw $123, -8256(%edx), %zmm6, %k5 # AVX512BW
+ vpcmpequw %zmm5, %zmm6, %k5 # AVX512BW
+ vpcmpleuw %zmm5, %zmm6, %k5 # AVX512BW
+ vpcmpltuw %zmm5, %zmm6, %k5 # AVX512BW
+ vpcmpnequw %zmm5, %zmm6, %k5 # AVX512BW
+ vpcmpnleuw %zmm5, %zmm6, %k5 # AVX512BW
+ vpcmpnltuw %zmm5, %zmm6, %k5 # AVX512BW
.intel_syntax noprefix
vpabsb zmm6, zmm5 # AVX512BW
--- 2017-11-10/gas/testsuite/gas/i386/avx512bw_vl-intel.d
+++ 2017-11-10/gas/testsuite/gas/i386/avx512bw_vl-intel.d
@@ -1271,6 +1271,18 @@ Disassembly of section \.text:
[ ]*[a-f0-9]+:[ ]*62 f3 4d 2f 3f aa 00 10 00 00 7b[ ]*vpcmpb k5\{k7\},ymm6,YMMWORD PTR \[edx\+0x1000\],0x7b
[ ]*[a-f0-9]+:[ ]*62 f3 4d 2f 3f 6a 80 7b[ ]*vpcmpb k5\{k7\},ymm6,YMMWORD PTR \[edx-0x1000\],0x7b
[ ]*[a-f0-9]+:[ ]*62 f3 4d 2f 3f aa e0 ef ff ff 7b[ ]*vpcmpb k5\{k7\},ymm6,YMMWORD PTR \[edx-0x1020\],0x7b
+[ ]*[a-f0-9]+:[ ]*62 f3 4d 08 3f ed 00[ ]*vpcmpeqb k5,xmm6,xmm5
+[ ]*[a-f0-9]+:[ ]*62 f3 4d 28 3f ed 00[ ]*vpcmpeqb k5,ymm6,ymm5
+[ ]*[a-f0-9]+:[ ]*62 f3 4d 08 3f ed 02[ ]*vpcmpleb k5,xmm6,xmm5
+[ ]*[a-f0-9]+:[ ]*62 f3 4d 28 3f ed 02[ ]*vpcmpleb k5,ymm6,ymm5
+[ ]*[a-f0-9]+:[ ]*62 f3 4d 08 3f ed 01[ ]*vpcmpltb k5,xmm6,xmm5
+[ ]*[a-f0-9]+:[ ]*62 f3 4d 28 3f ed 01[ ]*vpcmpltb k5,ymm6,ymm5
+[ ]*[a-f0-9]+:[ ]*62 f3 4d 08 3f ed 04[ ]*vpcmpneqb k5,xmm6,xmm5
+[ ]*[a-f0-9]+:[ ]*62 f3 4d 28 3f ed 04[ ]*vpcmpneqb k5,ymm6,ymm5
+[ ]*[a-f0-9]+:[ ]*62 f3 4d 08 3f ed 06[ ]*vpcmpnleb k5,xmm6,xmm5
+[ ]*[a-f0-9]+:[ ]*62 f3 4d 28 3f ed 06[ ]*vpcmpnleb k5,ymm6,ymm5
+[ ]*[a-f0-9]+:[ ]*62 f3 4d 08 3f ed 05[ ]*vpcmpnltb k5,xmm6,xmm5
+[ ]*[a-f0-9]+:[ ]*62 f3 4d 28 3f ed 05[ ]*vpcmpnltb k5,ymm6,ymm5
[ ]*[a-f0-9]+:[ ]*62 f3 cd 0f 3f ed ab[ ]*vpcmpw k5\{k7\},xmm6,xmm5,0xab
[ ]*[a-f0-9]+:[ ]*62 f3 cd 0f 3f ed 7b[ ]*vpcmpw k5\{k7\},xmm6,xmm5,0x7b
[ ]*[a-f0-9]+:[ ]*62 f3 cd 0f 3f 29 7b[ ]*vpcmpw k5\{k7\},xmm6,XMMWORD PTR \[ecx\],0x7b
@@ -1287,6 +1299,18 @@ Disassembly of section \.text:
[ ]*[a-f0-9]+:[ ]*62 f3 cd 2f 3f aa 00 10 00 00 7b[ ]*vpcmpw k5\{k7\},ymm6,YMMWORD PTR \[edx\+0x1000\],0x7b
[ ]*[a-f0-9]+:[ ]*62 f3 cd 2f 3f 6a 80 7b[ ]*vpcmpw k5\{k7\},ymm6,YMMWORD PTR \[edx-0x1000\],0x7b
[ ]*[a-f0-9]+:[ ]*62 f3 cd 2f 3f aa e0 ef ff ff 7b[ ]*vpcmpw k5\{k7\},ymm6,YMMWORD PTR \[edx-0x1020\],0x7b
+[ ]*[a-f0-9]+:[ ]*62 f3 cd 08 3f ed 00[ ]*vpcmpeqw k5,xmm6,xmm5
+[ ]*[a-f0-9]+:[ ]*62 f3 cd 28 3f ed 00[ ]*vpcmpeqw k5,ymm6,ymm5
+[ ]*[a-f0-9]+:[ ]*62 f3 cd 08 3f ed 02[ ]*vpcmplew k5,xmm6,xmm5
+[ ]*[a-f0-9]+:[ ]*62 f3 cd 28 3f ed 02[ ]*vpcmplew k5,ymm6,ymm5
+[ ]*[a-f0-9]+:[ ]*62 f3 cd 08 3f ed 01[ ]*vpcmpltw k5,xmm6,xmm5
+[ ]*[a-f0-9]+:[ ]*62 f3 cd 28 3f ed 01[ ]*vpcmpltw k5,ymm6,ymm5
+[ ]*[a-f0-9]+:[ ]*62 f3 cd 08 3f ed 04[ ]*vpcmpneqw k5,xmm6,xmm5
+[ ]*[a-f0-9]+:[ ]*62 f3 cd 28 3f ed 04[ ]*vpcmpneqw k5,ymm6,ymm5
+[ ]*[a-f0-9]+:[ ]*62 f3 cd 08 3f ed 06[ ]*vpcmpnlew k5,xmm6,xmm5
+[ ]*[a-f0-9]+:[ ]*62 f3 cd 28 3f ed 06[ ]*vpcmpnlew k5,ymm6,ymm5
+[ ]*[a-f0-9]+:[ ]*62 f3 cd 08 3f ed 05[ ]*vpcmpnltw k5,xmm6,xmm5
+[ ]*[a-f0-9]+:[ ]*62 f3 cd 28 3f ed 05[ ]*vpcmpnltw k5,ymm6,ymm5
[ ]*[a-f0-9]+:[ ]*62 f3 4d 0f 3e ed ab[ ]*vpcmpub k5\{k7\},xmm6,xmm5,0xab
[ ]*[a-f0-9]+:[ ]*62 f3 4d 0f 3e ed 7b[ ]*vpcmpub k5\{k7\},xmm6,xmm5,0x7b
[ ]*[a-f0-9]+:[ ]*62 f3 4d 0f 3e 29 7b[ ]*vpcmpub k5\{k7\},xmm6,XMMWORD PTR \[ecx\],0x7b
@@ -1303,6 +1327,18 @@ Disassembly of section \.text:
[ ]*[a-f0-9]+:[ ]*62 f3 4d 2f 3e aa 00 10 00 00 7b[ ]*vpcmpub k5\{k7\},ymm6,YMMWORD PTR \[edx\+0x1000\],0x7b
[ ]*[a-f0-9]+:[ ]*62 f3 4d 2f 3e 6a 80 7b[ ]*vpcmpub k5\{k7\},ymm6,YMMWORD PTR \[edx-0x1000\],0x7b
[ ]*[a-f0-9]+:[ ]*62 f3 4d 2f 3e aa e0 ef ff ff 7b[ ]*vpcmpub k5\{k7\},ymm6,YMMWORD PTR \[edx-0x1020\],0x7b
+[ ]*[a-f0-9]+:[ ]*62 f3 4d 08 3e ed 00[ ]*vpcmpequb k5,xmm6,xmm5
+[ ]*[a-f0-9]+:[ ]*62 f3 4d 28 3e ed 00[ ]*vpcmpequb k5,ymm6,ymm5
+[ ]*[a-f0-9]+:[ ]*62 f3 4d 08 3e ed 02[ ]*vpcmpleub k5,xmm6,xmm5
+[ ]*[a-f0-9]+:[ ]*62 f3 4d 28 3e ed 02[ ]*vpcmpleub k5,ymm6,ymm5
+[ ]*[a-f0-9]+:[ ]*62 f3 4d 08 3e ed 01[ ]*vpcmpltub k5,xmm6,xmm5
+[ ]*[a-f0-9]+:[ ]*62 f3 4d 28 3e ed 01[ ]*vpcmpltub k5,ymm6,ymm5
+[ ]*[a-f0-9]+:[ ]*62 f3 4d 08 3e ed 04[ ]*vpcmpnequb k5,xmm6,xmm5
+[ ]*[a-f0-9]+:[ ]*62 f3 4d 28 3e ed 04[ ]*vpcmpnequb k5,ymm6,ymm5
+[ ]*[a-f0-9]+:[ ]*62 f3 4d 08 3e ed 06[ ]*vpcmpnleub k5,xmm6,xmm5
+[ ]*[a-f0-9]+:[ ]*62 f3 4d 28 3e ed 06[ ]*vpcmpnleub k5,ymm6,ymm5
+[ ]*[a-f0-9]+:[ ]*62 f3 4d 08 3e ed 05[ ]*vpcmpnltub k5,xmm6,xmm5
+[ ]*[a-f0-9]+:[ ]*62 f3 4d 28 3e ed 05[ ]*vpcmpnltub k5,ymm6,ymm5
[ ]*[a-f0-9]+:[ ]*62 f3 cd 0f 3e ed ab[ ]*vpcmpuw k5\{k7\},xmm6,xmm5,0xab
[ ]*[a-f0-9]+:[ ]*62 f3 cd 0f 3e ed 7b[ ]*vpcmpuw k5\{k7\},xmm6,xmm5,0x7b
[ ]*[a-f0-9]+:[ ]*62 f3 cd 0f 3e 29 7b[ ]*vpcmpuw k5\{k7\},xmm6,XMMWORD PTR \[ecx\],0x7b
@@ -1319,6 +1355,18 @@ Disassembly of section \.text:
[ ]*[a-f0-9]+:[ ]*62 f3 cd 2f 3e aa 00 10 00 00 7b[ ]*vpcmpuw k5\{k7\},ymm6,YMMWORD PTR \[edx\+0x1000\],0x7b
[ ]*[a-f0-9]+:[ ]*62 f3 cd 2f 3e 6a 80 7b[ ]*vpcmpuw k5\{k7\},ymm6,YMMWORD PTR \[edx-0x1000\],0x7b
[ ]*[a-f0-9]+:[ ]*62 f3 cd 2f 3e aa e0 ef ff ff 7b[ ]*vpcmpuw k5\{k7\},ymm6,YMMWORD PTR \[edx-0x1020\],0x7b
+[ ]*[a-f0-9]+:[ ]*62 f3 cd 08 3e ed 00[ ]*vpcmpequw k5,xmm6,xmm5
+[ ]*[a-f0-9]+:[ ]*62 f3 cd 28 3e ed 00[ ]*vpcmpequw k5,ymm6,ymm5
+[ ]*[a-f0-9]+:[ ]*62 f3 cd 08 3e ed 02[ ]*vpcmpleuw k5,xmm6,xmm5
+[ ]*[a-f0-9]+:[ ]*62 f3 cd 28 3e ed 02[ ]*vpcmpleuw k5,ymm6,ymm5
+[ ]*[a-f0-9]+:[ ]*62 f3 cd 08 3e ed 01[ ]*vpcmpltuw k5,xmm6,xmm5
+[ ]*[a-f0-9]+:[ ]*62 f3 cd 28 3e ed 01[ ]*vpcmpltuw k5,ymm6,ymm5
+[ ]*[a-f0-9]+:[ ]*62 f3 cd 08 3e ed 04[ ]*vpcmpnequw k5,xmm6,xmm5
+[ ]*[a-f0-9]+:[ ]*62 f3 cd 28 3e ed 04[ ]*vpcmpnequw k5,ymm6,ymm5
+[ ]*[a-f0-9]+:[ ]*62 f3 cd 08 3e ed 06[ ]*vpcmpnleuw k5,xmm6,xmm5
+[ ]*[a-f0-9]+:[ ]*62 f3 cd 28 3e ed 06[ ]*vpcmpnleuw k5,ymm6,ymm5
+[ ]*[a-f0-9]+:[ ]*62 f3 cd 08 3e ed 05[ ]*vpcmpnltuw k5,xmm6,xmm5
+[ ]*[a-f0-9]+:[ ]*62 f3 cd 28 3e ed 05[ ]*vpcmpnltuw k5,ymm6,ymm5
[ ]*[a-f0-9]+:[ ]*62 f2 7d 0f 1c f5[ ]*vpabsb xmm6\{k7\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f2 7d 8f 1c f5[ ]*vpabsb xmm6\{k7\}\{z\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f2 7d 0f 1c 31[ ]*vpabsb xmm6\{k7\},XMMWORD PTR \[ecx\]
--- 2017-11-10/gas/testsuite/gas/i386/avx512bw_vl.d
+++ 2017-11-10/gas/testsuite/gas/i386/avx512bw_vl.d
@@ -1271,6 +1271,18 @@ Disassembly of section \.text:
[ ]*[a-f0-9]+:[ ]*62 f3 4d 2f 3f aa 00 10 00 00 7b[ ]*vpcmpb \$0x7b,0x1000\(%edx\),%ymm6,%k5\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f3 4d 2f 3f 6a 80 7b[ ]*vpcmpb \$0x7b,-0x1000\(%edx\),%ymm6,%k5\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f3 4d 2f 3f aa e0 ef ff ff 7b[ ]*vpcmpb \$0x7b,-0x1020\(%edx\),%ymm6,%k5\{%k7\}
+[ ]*[a-f0-9]+:[ ]*62 f3 4d 08 3f ed 00[ ]*vpcmpeqb %xmm5,%xmm6,%k5
+[ ]*[a-f0-9]+:[ ]*62 f3 4d 28 3f ed 00[ ]*vpcmpeqb %ymm5,%ymm6,%k5
+[ ]*[a-f0-9]+:[ ]*62 f3 4d 08 3f ed 02[ ]*vpcmpleb %xmm5,%xmm6,%k5
+[ ]*[a-f0-9]+:[ ]*62 f3 4d 28 3f ed 02[ ]*vpcmpleb %ymm5,%ymm6,%k5
+[ ]*[a-f0-9]+:[ ]*62 f3 4d 08 3f ed 01[ ]*vpcmpltb %xmm5,%xmm6,%k5
+[ ]*[a-f0-9]+:[ ]*62 f3 4d 28 3f ed 01[ ]*vpcmpltb %ymm5,%ymm6,%k5
+[ ]*[a-f0-9]+:[ ]*62 f3 4d 08 3f ed 04[ ]*vpcmpneqb %xmm5,%xmm6,%k5
+[ ]*[a-f0-9]+:[ ]*62 f3 4d 28 3f ed 04[ ]*vpcmpneqb %ymm5,%ymm6,%k5
+[ ]*[a-f0-9]+:[ ]*62 f3 4d 08 3f ed 06[ ]*vpcmpnleb %xmm5,%xmm6,%k5
+[ ]*[a-f0-9]+:[ ]*62 f3 4d 28 3f ed 06[ ]*vpcmpnleb %ymm5,%ymm6,%k5
+[ ]*[a-f0-9]+:[ ]*62 f3 4d 08 3f ed 05[ ]*vpcmpnltb %xmm5,%xmm6,%k5
+[ ]*[a-f0-9]+:[ ]*62 f3 4d 28 3f ed 05[ ]*vpcmpnltb %ymm5,%ymm6,%k5
[ ]*[a-f0-9]+:[ ]*62 f3 cd 0f 3f ed ab[ ]*vpcmpw \$0xab,%xmm5,%xmm6,%k5\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f3 cd 0f 3f ed 7b[ ]*vpcmpw \$0x7b,%xmm5,%xmm6,%k5\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f3 cd 0f 3f 29 7b[ ]*vpcmpw \$0x7b,\(%ecx\),%xmm6,%k5\{%k7\}
@@ -1287,6 +1299,18 @@ Disassembly of section \.text:
[ ]*[a-f0-9]+:[ ]*62 f3 cd 2f 3f aa 00 10 00 00 7b[ ]*vpcmpw \$0x7b,0x1000\(%edx\),%ymm6,%k5\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f3 cd 2f 3f 6a 80 7b[ ]*vpcmpw \$0x7b,-0x1000\(%edx\),%ymm6,%k5\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f3 cd 2f 3f aa e0 ef ff ff 7b[ ]*vpcmpw \$0x7b,-0x1020\(%edx\),%ymm6,%k5\{%k7\}
+[ ]*[a-f0-9]+:[ ]*62 f3 cd 08 3f ed 00[ ]*vpcmpeqw %xmm5,%xmm6,%k5
+[ ]*[a-f0-9]+:[ ]*62 f3 cd 28 3f ed 00[ ]*vpcmpeqw %ymm5,%ymm6,%k5
+[ ]*[a-f0-9]+:[ ]*62 f3 cd 08 3f ed 02[ ]*vpcmplew %xmm5,%xmm6,%k5
+[ ]*[a-f0-9]+:[ ]*62 f3 cd 28 3f ed 02[ ]*vpcmplew %ymm5,%ymm6,%k5
+[ ]*[a-f0-9]+:[ ]*62 f3 cd 08 3f ed 01[ ]*vpcmpltw %xmm5,%xmm6,%k5
+[ ]*[a-f0-9]+:[ ]*62 f3 cd 28 3f ed 01[ ]*vpcmpltw %ymm5,%ymm6,%k5
+[ ]*[a-f0-9]+:[ ]*62 f3 cd 08 3f ed 04[ ]*vpcmpneqw %xmm5,%xmm6,%k5
+[ ]*[a-f0-9]+:[ ]*62 f3 cd 28 3f ed 04[ ]*vpcmpneqw %ymm5,%ymm6,%k5
+[ ]*[a-f0-9]+:[ ]*62 f3 cd 08 3f ed 06[ ]*vpcmpnlew %xmm5,%xmm6,%k5
+[ ]*[a-f0-9]+:[ ]*62 f3 cd 28 3f ed 06[ ]*vpcmpnlew %ymm5,%ymm6,%k5
+[ ]*[a-f0-9]+:[ ]*62 f3 cd 08 3f ed 05[ ]*vpcmpnltw %xmm5,%xmm6,%k5
+[ ]*[a-f0-9]+:[ ]*62 f3 cd 28 3f ed 05[ ]*vpcmpnltw %ymm5,%ymm6,%k5
[ ]*[a-f0-9]+:[ ]*62 f3 4d 0f 3e ed ab[ ]*vpcmpub \$0xab,%xmm5,%xmm6,%k5\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f3 4d 0f 3e ed 7b[ ]*vpcmpub \$0x7b,%xmm5,%xmm6,%k5\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f3 4d 0f 3e 29 7b[ ]*vpcmpub \$0x7b,\(%ecx\),%xmm6,%k5\{%k7\}
@@ -1303,6 +1327,18 @@ Disassembly of section \.text:
[ ]*[a-f0-9]+:[ ]*62 f3 4d 2f 3e aa 00 10 00 00 7b[ ]*vpcmpub \$0x7b,0x1000\(%edx\),%ymm6,%k5\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f3 4d 2f 3e 6a 80 7b[ ]*vpcmpub \$0x7b,-0x1000\(%edx\),%ymm6,%k5\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f3 4d 2f 3e aa e0 ef ff ff 7b[ ]*vpcmpub \$0x7b,-0x1020\(%edx\),%ymm6,%k5\{%k7\}
+[ ]*[a-f0-9]+:[ ]*62 f3 4d 08 3e ed 00[ ]*vpcmpequb %xmm5,%xmm6,%k5
+[ ]*[a-f0-9]+:[ ]*62 f3 4d 28 3e ed 00[ ]*vpcmpequb %ymm5,%ymm6,%k5
+[ ]*[a-f0-9]+:[ ]*62 f3 4d 08 3e ed 02[ ]*vpcmpleub %xmm5,%xmm6,%k5
+[ ]*[a-f0-9]+:[ ]*62 f3 4d 28 3e ed 02[ ]*vpcmpleub %ymm5,%ymm6,%k5
+[ ]*[a-f0-9]+:[ ]*62 f3 4d 08 3e ed 01[ ]*vpcmpltub %xmm5,%xmm6,%k5
+[ ]*[a-f0-9]+:[ ]*62 f3 4d 28 3e ed 01[ ]*vpcmpltub %ymm5,%ymm6,%k5
+[ ]*[a-f0-9]+:[ ]*62 f3 4d 08 3e ed 04[ ]*vpcmpnequb %xmm5,%xmm6,%k5
+[ ]*[a-f0-9]+:[ ]*62 f3 4d 28 3e ed 04[ ]*vpcmpnequb %ymm5,%ymm6,%k5
+[ ]*[a-f0-9]+:[ ]*62 f3 4d 08 3e ed 06[ ]*vpcmpnleub %xmm5,%xmm6,%k5
+[ ]*[a-f0-9]+:[ ]*62 f3 4d 28 3e ed 06[ ]*vpcmpnleub %ymm5,%ymm6,%k5
+[ ]*[a-f0-9]+:[ ]*62 f3 4d 08 3e ed 05[ ]*vpcmpnltub %xmm5,%xmm6,%k5
+[ ]*[a-f0-9]+:[ ]*62 f3 4d 28 3e ed 05[ ]*vpcmpnltub %ymm5,%ymm6,%k5
[ ]*[a-f0-9]+:[ ]*62 f3 cd 0f 3e ed ab[ ]*vpcmpuw \$0xab,%xmm5,%xmm6,%k5\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f3 cd 0f 3e ed 7b[ ]*vpcmpuw \$0x7b,%xmm5,%xmm6,%k5\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f3 cd 0f 3e 29 7b[ ]*vpcmpuw \$0x7b,\(%ecx\),%xmm6,%k5\{%k7\}
@@ -1319,6 +1355,18 @@ Disassembly of section \.text:
[ ]*[a-f0-9]+:[ ]*62 f3 cd 2f 3e aa 00 10 00 00 7b[ ]*vpcmpuw \$0x7b,0x1000\(%edx\),%ymm6,%k5\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f3 cd 2f 3e 6a 80 7b[ ]*vpcmpuw \$0x7b,-0x1000\(%edx\),%ymm6,%k5\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f3 cd 2f 3e aa e0 ef ff ff 7b[ ]*vpcmpuw \$0x7b,-0x1020\(%edx\),%ymm6,%k5\{%k7\}
+[ ]*[a-f0-9]+:[ ]*62 f3 cd 08 3e ed 00[ ]*vpcmpequw %xmm5,%xmm6,%k5
+[ ]*[a-f0-9]+:[ ]*62 f3 cd 28 3e ed 00[ ]*vpcmpequw %ymm5,%ymm6,%k5
+[ ]*[a-f0-9]+:[ ]*62 f3 cd 08 3e ed 02[ ]*vpcmpleuw %xmm5,%xmm6,%k5
+[ ]*[a-f0-9]+:[ ]*62 f3 cd 28 3e ed 02[ ]*vpcmpleuw %ymm5,%ymm6,%k5
+[ ]*[a-f0-9]+:[ ]*62 f3 cd 08 3e ed 01[ ]*vpcmpltuw %xmm5,%xmm6,%k5
+[ ]*[a-f0-9]+:[ ]*62 f3 cd 28 3e ed 01[ ]*vpcmpltuw %ymm5,%ymm6,%k5
+[ ]*[a-f0-9]+:[ ]*62 f3 cd 08 3e ed 04[ ]*vpcmpnequw %xmm5,%xmm6,%k5
+[ ]*[a-f0-9]+:[ ]*62 f3 cd 28 3e ed 04[ ]*vpcmpnequw %ymm5,%ymm6,%k5
+[ ]*[a-f0-9]+:[ ]*62 f3 cd 08 3e ed 06[ ]*vpcmpnleuw %xmm5,%xmm6,%k5
+[ ]*[a-f0-9]+:[ ]*62 f3 cd 28 3e ed 06[ ]*vpcmpnleuw %ymm5,%ymm6,%k5
+[ ]*[a-f0-9]+:[ ]*62 f3 cd 08 3e ed 05[ ]*vpcmpnltuw %xmm5,%xmm6,%k5
+[ ]*[a-f0-9]+:[ ]*62 f3 cd 28 3e ed 05[ ]*vpcmpnltuw %ymm5,%ymm6,%k5
[ ]*[a-f0-9]+:[ ]*62 f2 7d 0f 1c f5[ ]*vpabsb %xmm5,%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 7d 8f 1c f5[ ]*vpabsb %xmm5,%xmm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f2 7d 0f 1c 31[ ]*vpabsb \(%ecx\),%xmm6\{%k7\}
--- 2017-11-10/gas/testsuite/gas/i386/avx512bw_vl.s
+++ 2017-11-10/gas/testsuite/gas/i386/avx512bw_vl.s
@@ -1265,6 +1265,18 @@ _start:
vpcmpb $123, 4096(%edx), %ymm6, %k5{%k7} # AVX512{BW,VL}
vpcmpb $123, -4096(%edx), %ymm6, %k5{%k7} # AVX512{BW,VL} Disp8
vpcmpb $123, -4128(%edx), %ymm6, %k5{%k7} # AVX512{BW,VL}
+ vpcmpb $0, %xmm5, %xmm6, %k5 # AVX512{BW,VL}
+ vpcmpb $0, %ymm5, %ymm6, %k5 # AVX512{BW,VL}
+ vpcmpleb %xmm5, %xmm6, %k5 # AVX512{BW,VL}
+ vpcmpleb %ymm5, %ymm6, %k5 # AVX512{BW,VL}
+ vpcmpltb %xmm5, %xmm6, %k5 # AVX512{BW,VL}
+ vpcmpltb %ymm5, %ymm6, %k5 # AVX512{BW,VL}
+ vpcmpneqb %xmm5, %xmm6, %k5 # AVX512{BW,VL}
+ vpcmpneqb %ymm5, %ymm6, %k5 # AVX512{BW,VL}
+ vpcmpnleb %xmm5, %xmm6, %k5 # AVX512{BW,VL}
+ vpcmpnleb %ymm5, %ymm6, %k5 # AVX512{BW,VL}
+ vpcmpnltb %xmm5, %xmm6, %k5 # AVX512{BW,VL}
+ vpcmpnltb %ymm5, %ymm6, %k5 # AVX512{BW,VL}
vpcmpw $0xab, %xmm5, %xmm6, %k5{%k7} # AVX512{BW,VL}
vpcmpw $123, %xmm5, %xmm6, %k5{%k7} # AVX512{BW,VL}
vpcmpw $123, (%ecx), %xmm6, %k5{%k7} # AVX512{BW,VL}
@@ -1281,6 +1293,18 @@ _start:
vpcmpw $123, 4096(%edx), %ymm6, %k5{%k7} # AVX512{BW,VL}
vpcmpw $123, -4096(%edx), %ymm6, %k5{%k7} # AVX512{BW,VL} Disp8
vpcmpw $123, -4128(%edx), %ymm6, %k5{%k7} # AVX512{BW,VL}
+ vpcmpw $0, %xmm5, %xmm6, %k5 # AVX512{BW,VL}
+ vpcmpw $0, %ymm5, %ymm6, %k5 # AVX512{BW,VL}
+ vpcmplew %xmm5, %xmm6, %k5 # AVX512{BW,VL}
+ vpcmplew %ymm5, %ymm6, %k5 # AVX512{BW,VL}
+ vpcmpltw %xmm5, %xmm6, %k5 # AVX512{BW,VL}
+ vpcmpltw %ymm5, %ymm6, %k5 # AVX512{BW,VL}
+ vpcmpneqw %xmm5, %xmm6, %k5 # AVX512{BW,VL}
+ vpcmpneqw %ymm5, %ymm6, %k5 # AVX512{BW,VL}
+ vpcmpnlew %xmm5, %xmm6, %k5 # AVX512{BW,VL}
+ vpcmpnlew %ymm5, %ymm6, %k5 # AVX512{BW,VL}
+ vpcmpnltw %xmm5, %xmm6, %k5 # AVX512{BW,VL}
+ vpcmpnltw %ymm5, %ymm6, %k5 # AVX512{BW,VL}
vpcmpub $0xab, %xmm5, %xmm6, %k5{%k7} # AVX512{BW,VL}
vpcmpub $123, %xmm5, %xmm6, %k5{%k7} # AVX512{BW,VL}
vpcmpub $123, (%ecx), %xmm6, %k5{%k7} # AVX512{BW,VL}
@@ -1297,6 +1321,18 @@ _start:
vpcmpub $123, 4096(%edx), %ymm6, %k5{%k7} # AVX512{BW,VL}
vpcmpub $123, -4096(%edx), %ymm6, %k5{%k7} # AVX512{BW,VL} Disp8
vpcmpub $123, -4128(%edx), %ymm6, %k5{%k7} # AVX512{BW,VL}
+ vpcmpub $0, %xmm5, %xmm6, %k5 # AVX512{BW,VL}
+ vpcmpub $0, %ymm5, %ymm6, %k5 # AVX512{BW,VL}
+ vpcmpleub %xmm5, %xmm6, %k5 # AVX512{BW,VL}
+ vpcmpleub %ymm5, %ymm6, %k5 # AVX512{BW,VL}
+ vpcmpltub %xmm5, %xmm6, %k5 # AVX512{BW,VL}
+ vpcmpltub %ymm5, %ymm6, %k5 # AVX512{BW,VL}
+ vpcmpnequb %xmm5, %xmm6, %k5 # AVX512{BW,VL}
+ vpcmpnequb %ymm5, %ymm6, %k5 # AVX512{BW,VL}
+ vpcmpnleub %xmm5, %xmm6, %k5 # AVX512{BW,VL}
+ vpcmpnleub %ymm5, %ymm6, %k5 # AVX512{BW,VL}
+ vpcmpnltub %xmm5, %xmm6, %k5 # AVX512{BW,VL}
+ vpcmpnltub %ymm5, %ymm6, %k5 # AVX512{BW,VL}
vpcmpuw $0xab, %xmm5, %xmm6, %k5{%k7} # AVX512{BW,VL}
vpcmpuw $123, %xmm5, %xmm6, %k5{%k7} # AVX512{BW,VL}
vpcmpuw $123, (%ecx), %xmm6, %k5{%k7} # AVX512{BW,VL}
@@ -1313,6 +1349,18 @@ _start:
vpcmpuw $123, 4096(%edx), %ymm6, %k5{%k7} # AVX512{BW,VL}
vpcmpuw $123, -4096(%edx), %ymm6, %k5{%k7} # AVX512{BW,VL} Disp8
vpcmpuw $123, -4128(%edx), %ymm6, %k5{%k7} # AVX512{BW,VL}
+ vpcmpuw $0, %xmm5, %xmm6, %k5 # AVX512{BW,VL}
+ vpcmpuw $0, %ymm5, %ymm6, %k5 # AVX512{BW,VL}
+ vpcmpleuw %xmm5, %xmm6, %k5 # AVX512{BW,VL}
+ vpcmpleuw %ymm5, %ymm6, %k5 # AVX512{BW,VL}
+ vpcmpltuw %xmm5, %xmm6, %k5 # AVX512{BW,VL}
+ vpcmpltuw %ymm5, %ymm6, %k5 # AVX512{BW,VL}
+ vpcmpnequw %xmm5, %xmm6, %k5 # AVX512{BW,VL}
+ vpcmpnequw %ymm5, %ymm6, %k5 # AVX512{BW,VL}
+ vpcmpnleuw %xmm5, %xmm6, %k5 # AVX512{BW,VL}
+ vpcmpnleuw %ymm5, %ymm6, %k5 # AVX512{BW,VL}
+ vpcmpnltuw %xmm5, %xmm6, %k5 # AVX512{BW,VL}
+ vpcmpnltuw %ymm5, %ymm6, %k5 # AVX512{BW,VL}
.intel_syntax noprefix
vpabsb xmm6{k7}, xmm5 # AVX512{BW,VL}
--- 2017-11-10/opcodes/i386-dis-evex.h
+++ 2017-11-10/opcodes/i386-dis-evex.h
@@ -3957,13 +3957,13 @@ static const struct dis386 evex_table[][
},
/* EVEX_W_0F3A3E_P_2 */
{
- { "vpcmpub", { XMask, Vex, EXx, Ib }, 0 },
- { "vpcmpuw", { XMask, Vex, EXx, Ib }, 0 },
+ { "vpcmpub", { XMask, Vex, EXx, VPCMP }, 0 },
+ { "vpcmpuw", { XMask, Vex, EXx, VPCMP }, 0 },
},
/* EVEX_W_0F3A3F_P_2 */
{
- { "vpcmpb", { XMask, Vex, EXx, Ib }, 0 },
- { "vpcmpw", { XMask, Vex, EXx, Ib }, 0 },
+ { "vpcmpb", { XMask, Vex, EXx, VPCMP }, 0 },
+ { "vpcmpw", { XMask, Vex, EXx, VPCMP }, 0 },
},
/* EVEX_W_0F3A42_P_2 */
{
--- 2017-11-10/opcodes/i386-opc.tbl
+++ 2017-11-10/opcodes/i386-opc.tbl
@@ -5595,19 +5595,104 @@ vpbroadcastw, 2, 0x667B, None, 1, CpuAVX
vpbroadcastw, 2, 0x667B, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Reg32, RegXMM }
vpbroadcastw, 2, 0x667B, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Reg32, RegYMM }
+vpcmpeqb, 3, 0x6674, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegMask }
+vpcmpeqb, 3, 0x6674, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
+vpcmpeqb, 3, 0x6674, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
+vpcmpgtb, 3, 0x6664, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegMask }
+vpcmpgtb, 3, 0x6664, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
+vpcmpgtb, 3, 0x6664, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vpcmpb, 4, 0x663F, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegMask }
vpcmpb, 4, 0x663F, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vpcmpb, 4, 0x663F, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
+vpcmpeqb, 3, 0x663F, 0, 1, CpuAVX512BW, Modrm|EVex=1|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegMask }
+vpcmpeqb, 3, 0x663F, 0, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
+vpcmpeqb, 3, 0x663F, 0, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
+vpcmpleb, 3, 0x663F, 2, 1, CpuAVX512BW, Modrm|EVex=1|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegMask }
+vpcmpleb, 3, 0x663F, 2, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
+vpcmpleb, 3, 0x663F, 2, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
+vpcmpltb, 3, 0x663F, 1, 1, CpuAVX512BW, Modrm|EVex=1|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegMask }
+vpcmpltb, 3, 0x663F, 1, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
+vpcmpltb, 3, 0x663F, 1, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
+vpcmpneqb, 3, 0x663F, 4, 1, CpuAVX512BW, Modrm|EVex=1|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegMask }
+vpcmpneqb, 3, 0x663F, 4, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
+vpcmpneqb, 3, 0x663F, 4, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
+vpcmpnleb, 3, 0x663F, 6, 1, CpuAVX512BW, Modrm|EVex=1|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegMask }
+vpcmpnleb, 3, 0x663F, 6, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
+vpcmpnleb, 3, 0x663F, 6, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
+vpcmpnltb, 3, 0x663F, 5, 1, CpuAVX512BW, Modrm|EVex=1|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegMask }
+vpcmpnltb, 3, 0x663F, 5, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
+vpcmpnltb, 3, 0x663F, 5, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vpcmpub, 4, 0x663E, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegMask }
vpcmpub, 4, 0x663E, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vpcmpub, 4, 0x663E, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
+vpcmpequb, 3, 0x663E, 0, 1, CpuAVX512BW, Modrm|EVex=1|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegMask }
+vpcmpequb, 3, 0x663E, 0, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
+vpcmpequb, 3, 0x663E, 0, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
+vpcmpleub, 3, 0x663E, 2, 1, CpuAVX512BW, Modrm|EVex=1|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegMask }
+vpcmpleub, 3, 0x663E, 2, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
+vpcmpleub, 3, 0x663E, 2, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
+vpcmpltub, 3, 0x663E, 1, 1, CpuAVX512BW, Modrm|EVex=1|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegMask }
+vpcmpltub, 3, 0x663E, 1, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
+vpcmpltub, 3, 0x663E, 1, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
+vpcmpnequb, 3, 0x663E, 4, 1, CpuAVX512BW, Modrm|EVex=1|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegMask }
+vpcmpnequb, 3, 0x663E, 4, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
+vpcmpnequb, 3, 0x663E, 4, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
+vpcmpnleub, 3, 0x663E, 6, 1, CpuAVX512BW, Modrm|EVex=1|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegMask }
+vpcmpnleub, 3, 0x663E, 6, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
+vpcmpnleub, 3, 0x663E, 6, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
+vpcmpnltub, 3, 0x663E, 5, 1, CpuAVX512BW, Modrm|EVex=1|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegMask }
+vpcmpnltub, 3, 0x663E, 5, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
+vpcmpnltub, 3, 0x663E, 5, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
+
+vpcmpeqw, 3, 0x6675, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegMask }
+vpcmpeqw, 3, 0x6675, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
+vpcmpeqw, 3, 0x6675, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
+vpcmpgtw, 3, 0x6665, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegMask }
+vpcmpgtw, 3, 0x6665, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
+vpcmpgtw, 3, 0x6665, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
+vpcmpw, 4, 0x663F, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegMask }
+vpcmpw, 4, 0x663F, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
+vpcmpw, 4, 0x663F, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
+vpcmpeqw, 3, 0x663F, 0, 1, CpuAVX512BW, Modrm|EVex=1|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegMask }
+vpcmpeqw, 3, 0x663F, 0, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
+vpcmpeqw, 3, 0x663F, 0, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
+vpcmplew, 3, 0x663F, 2, 1, CpuAVX512BW, Modrm|EVex=1|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegMask }
+vpcmplew, 3, 0x663F, 2, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
+vpcmplew, 3, 0x663F, 2, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
+vpcmpltw, 3, 0x663F, 1, 1, CpuAVX512BW, Modrm|EVex=1|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegMask }
+vpcmpltw, 3, 0x663F, 1, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
+vpcmpltw, 3, 0x663F, 1, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
+vpcmpneqw, 3, 0x663F, 4, 1, CpuAVX512BW, Modrm|EVex=1|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegMask }
+vpcmpneqw, 3, 0x663F, 4, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
+vpcmpneqw, 3, 0x663F, 4, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
+vpcmpnlew, 3, 0x663F, 6, 1, CpuAVX512BW, Modrm|EVex=1|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegMask }
+vpcmpnlew, 3, 0x663F, 6, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
+vpcmpnlew, 3, 0x663F, 6, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
+vpcmpnltw, 3, 0x663F, 5, 1, CpuAVX512BW, Modrm|EVex=1|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegMask }
+vpcmpnltw, 3, 0x663F, 5, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
+vpcmpnltw, 3, 0x663F, 5, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
+vpcmpuw, 4, 0x663E, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegMask }
+vpcmpuw, 4, 0x663E, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
+vpcmpuw, 4, 0x663E, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
+vpcmpequw, 3, 0x663E, 0, 1, CpuAVX512BW, Modrm|EVex=1|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegMask }
+vpcmpequw, 3, 0x663E, 0, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
+vpcmpequw, 3, 0x663E, 0, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
+vpcmpleuw, 3, 0x663E, 2, 1, CpuAVX512BW, Modrm|EVex=1|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegMask }
+vpcmpleuw, 3, 0x663E, 2, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
+vpcmpleuw, 3, 0x663E, 2, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
+vpcmpltuw, 3, 0x663E, 1, 1, CpuAVX512BW, Modrm|EVex=1|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegMask }
+vpcmpltuw, 3, 0x663E, 1, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
+vpcmpltuw, 3, 0x663E, 1, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
+vpcmpnequw, 3, 0x663E, 4, 1, CpuAVX512BW, Modrm|EVex=1|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegMask }
+vpcmpnequw, 3, 0x663E, 4, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
+vpcmpnequw, 3, 0x663E, 4, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
+vpcmpnleuw, 3, 0x663E, 6, 1, CpuAVX512BW, Modrm|EVex=1|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegMask }
+vpcmpnleuw, 3, 0x663E, 6, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
+vpcmpnleuw, 3, 0x663E, 6, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
+vpcmpnltuw, 3, 0x663E, 5, 1, CpuAVX512BW, Modrm|EVex=1|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegMask }
+vpcmpnltuw, 3, 0x663E, 5, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
+vpcmpnltuw, 3, 0x663E, 5, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
-vpcmpeqb, 3, 0x6674, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegMask }
-vpcmpeqb, 3, 0x6674, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
-vpcmpeqb, 3, 0x6674, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
-vpcmpgtb, 3, 0x6664, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegMask }
-vpcmpgtb, 3, 0x6664, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
-vpcmpgtb, 3, 0x6664, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vpslldq, 3, 0x6673, 7, 1, CpuAVX512BW, Modrm|EVex=1|VexOpcode=0|VexVVVV=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegZMM, RegZMM }
vpslldq, 3, 0x6673, 7, 1, CpuAVX512BW, Modrm|EVex=1|VexOpcode=0|VexVVVV=3|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM }
vpslldq, 3, 0x6673, 7, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|VexOpcode=0|VexVVVV=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, RegXMM }
@@ -5621,22 +5706,9 @@ vpsrldq, 3, 0x6673, 3, 1, CpuAVX512BW|Cp
vpsrldq, 3, 0x6673, 3, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|VexOpcode=0|VexVVVV=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM, RegYMM }
vpsrldq, 3, 0x6673, 3, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|VexOpcode=0|VexVVVV=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM }
-vpcmpeqw, 3, 0x6675, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegMask }
-vpcmpeqw, 3, 0x6675, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
-vpcmpeqw, 3, 0x6675, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
-vpcmpgtw, 3, 0x6665, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegMask }
-vpcmpgtw, 3, 0x6665, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
-vpcmpgtw, 3, 0x6665, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vpextrw, 3, 0x66C5, None, 1, CpuAVX512BW, Modrm|EVex=4|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg32|Reg64 }
vpinsrw, 4, 0x66C4, None, 1, CpuAVX512BW, Modrm|EVex=4|VexOpcode=0|VexVVVV=1|Disp8MemShift=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Reg32|Reg64|Word|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
-vpcmpuw, 4, 0x663E, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegMask }
-vpcmpuw, 4, 0x663E, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
-vpcmpuw, 4, 0x663E, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
-vpcmpw, 4, 0x663F, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegMask }
-vpcmpw, 4, 0x663F, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
-vpcmpw, 4, 0x663F, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
-
vpextrb, 3, 0x6614, None, 1, CpuAVX512BW, Modrm|EVex=4|VexOpcode=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg32|Reg64|Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
vpinsrb, 4, 0x6620, None, 1, CpuAVX512BW, Modrm|EVex=4|VexOpcode=2|VexVVVV=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Reg32|Reg64|Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM }