Re: [PATCH v2] x86: ignore high register select bit(s) in 32- and 16-bit modes

["H.J. Lu" <hjl dot tools at gmail dot com>]

On Tue, Nov 14, 2017 at 11:57 PM, Jan Beulich <JBeulich@suse.com> wrote:
> While commits 9889cbb14e ("Check invalid mask registers") and
> abfcb414b9 ("X86: Ignore REX_B bit for 32-bit XOP instructions") went a
> bit into the right direction, this wasn't quite enough:
> - VEX.vvvv has its high bit ignored
> - EVEX.vvvv has its high bit ignored together with EVEX.v'
> - the high bits of {,E}VEX.vvvv should not be prematurely zapped, to
>   allow proper checking of them when the fields has to hold al ones
> - when the high bits of an immediate specify a register, bit 7 is
>   ignored
> ---
> v2: Parts of the test were moved to earlier, already approved (and
>     committed) patches.
>
> gas/
> 2017-11-15  Jan Beulich  <jbeulich@suse.com>
>
>         * testsuite/gas/i386/noextreg.s: Add tests with register index
>         bit 3 set.
>         * testsuite/gas/i386/noextreg.d: Adjust expectations.
>
> opcodes/
> 2017-11-15  Jan Beulich  <jbeulich@suse.com>
>
>         (get_valid_dis386): Never flag bad opcode when
>         vex.register_specifier is beyond 7. Always store all four
>         bits of it. Move 16-/32-bit override in EVEX handling after
>         all to be overridden bits have been set.
>         (OP_VEX): Mask vex.register_specifier outside of 64-bit mode.
>         Use rex to determine GPR register set.
>         (OP_EX_VexReg, OP_Vex_2src_1, OP_Vex_2src_2, OP_REG_VexI4,
>         OP_LWP_E): Mask vex.register_specifier outside of 64-bit mode.
>

This is OK.

Thanks.

-- 
H.J.