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[PATCH, GAS] Add new macro for Thumb-only opcodes
- From: Thomas Preudhomme <thomas dot preudhomme at foss dot arm dot com>
- To: Richard Earnshaw <richard dot earnshaw at arm dot com>, Nick Clifton <nickc at redhat dot com>, Alan Modra <amodra at gmail dot com>, "binutils at sourceware dot org" <binutils at sourceware dot org>
- Date: Fri, 1 Dec 2017 14:50:46 +0000
- Subject: [PATCH, GAS] Add new macro for Thumb-only opcodes
- Authentication-results: sourceware.org; auth=none
- References: <f5ce1db9-6e36-84e8-66bc-1549a1a90951@foss.arm.com> <0df79b37-ad12-8c76-53fd-fa2a0d30f9bf@foss.arm.com>
Hi,
Armv8-M Security Extensions introduced some Thumb-only opcodes
(eg. sg). These are defined using the TUE and TCE macros, setting the
Arm execution state related fields to 0/NULL.
This patch adds 2 new macros to avoid filling this field and clearly
identify Thumb-only instructions.
ChangeLog entry is as follows:
*** gas/ChangeLog ***
2017-11-13 Thomas Preud'homme <thomas.preudhomme@arm.com>
* config/tc-arm.c (ToC): Define macro.
(ToU): Likewise.
(insns): Make use of above macros for new instructions introduced in
Armv8-M.
Testing: Testsuite run while targeting arm-none-eabi systems shows no
regression.
Is this ok for master branch?
Best regards,
Thomas
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 17eded3524fad042b65434c4a783de4ec69c4ade..c304fa61769e6de8a9278fe6fcb5b2f174e614c0 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -19395,6 +19395,17 @@ static struct asm_barrier_opt barrier_opt_names[] =
#define C3(mnem, op, nops, ops, ae) \
{ #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
+/* Thumb-only variants of TCE and TUE. */
+#define ToC(mnem, top, nops, ops, te) \
+ { mnem, OPS##nops ops, OT_csuffix, 0x0, 0x##top, 0, THUMB_VARIANT, NULL, \
+ do_##te }
+ //TCE (mnem, 0, top, nops, ops, NULL, te)
+
+#define ToU(mnem, top, nops, ops, te) \
+ { mnem, OPS##nops ops, OT_unconditional, 0x0, 0x##top, 0, THUMB_VARIANT, \
+ NULL, do_##te }
+ //TUE(mnem, 0, top, nops, ops, NULL, te)
+
/* Legacy mnemonics that always have conditional infix after the third
character. */
#define CL(mnem, op, nops, ops, ae) \
@@ -21429,20 +21440,20 @@ static const struct asm_opcode insns[] =
#define ARM_VARIANT NULL
#undef THUMB_VARIANT
#define THUMB_VARIANT & arm_ext_v8m
- TUE("sg", 0, e97fe97f, 0, (), 0, noargs),
- TCE("blxns", 0, 4784, 1, (RRnpc), 0, t_blx),
- TCE("bxns", 0, 4704, 1, (RRnpc), 0, t_bx),
- TCE("tt", 0, e840f000, 2, (RRnpc, RRnpc), 0, tt),
- TCE("ttt", 0, e840f040, 2, (RRnpc, RRnpc), 0, tt),
- TCE("tta", 0, e840f080, 2, (RRnpc, RRnpc), 0, tt),
- TCE("ttat", 0, e840f0c0, 2, (RRnpc, RRnpc), 0, tt),
+ ToU("sg", e97fe97f, 0, (), noargs),
+ ToC("blxns", 4784, 1, (RRnpc), t_blx),
+ ToC("bxns", 4704, 1, (RRnpc), t_bx),
+ ToC("tt", e840f000, 2, (RRnpc, RRnpc), tt),
+ ToC("ttt", e840f040, 2, (RRnpc, RRnpc), tt),
+ ToC("tta", e840f080, 2, (RRnpc, RRnpc), tt),
+ ToC("ttat", e840f0c0, 2, (RRnpc, RRnpc), tt),
/* FP for ARMv8-M Mainline. Enabled for ARMv8-M Mainline because the
instructions behave as nop if no VFP is present. */
#undef THUMB_VARIANT
#define THUMB_VARIANT & arm_ext_v8m_main
- TCE("vlldm", 0, ec300a00, 1, (RRnpc), 0, rn),
- TCE("vlstm", 0, ec200a00, 1, (RRnpc), 0, rn),
+ ToC("vlldm", ec300a00, 1, (RRnpc), rn),
+ ToC("vlstm", ec200a00, 1, (RRnpc), rn),
};
#undef ARM_VARIANT
#undef THUMB_VARIANT