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[PATCH 1/4] x86: replace Reg8, Reg16, Reg32, and Reg64
- From: "Jan Beulich" <JBeulich at suse dot com>
- To: <binutils at sourceware dot org>
- Cc: "H.J. Lu" <hjl dot tools at gmail dot com>
- Date: Fri, 15 Dec 2017 03:32:14 -0700
- Subject: [PATCH 1/4] x86: replace Reg8, Reg16, Reg32, and Reg64
- Authentication-results: sourceware.org; auth=none
- References: <5A33A9D802000078001979BE@prv-mh.provo.novell.com>
Use a combination of a single new Reg bit and Byte, Word, Dword, or
Qword instead.
Besides shrinking the number of operand type bits this has the benefit
of making register handling more similar to accumulator handling (a
generic flag is being accompanied by a "size qualifier"). It requires,
however, to split a few insn templates, as it is no longer correct to
have combinations like Reg32|Reg64|Byte. This slight growth in size will
hopefully be outweighed by this change paving the road for folding a
presumably much larger number of templates later on.
gas/
2017-12-15 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (operand_type_check, pi): Switch .reg<N> to
just .reg.
(operand_size_match): Qualify .anysize check with .reg one.
Extend .acc check to also cover .reg.
(operand_type_register_match): Drop m0 and m1 parameters. Switch
.reg<N> to .byte/.word/.dword/.qword. Drop .acc special
handling.
(md_assemble): Expand .reg8 checks to .reg plus .bytes ones.
(optimize_imm, process_suffix, check_byte_reg, check_long_reg,
check_qword_reg, check_word_reg): Expand .reg<N> checks to .reg
plus size ones.
(match_template): Drop arguments from calls to
operand_type_register_match().
(build_modrm_byte, i386_addressing_mode, i386_index_check,
parse_real_register): Replace .reg<N> checks.
* config/tc-i386-intel.c (i386_intel_simplify,
i386_intel_operand): Switch .reg16 to .word.
opcodes/
2017-12-15 Jan Beulich <jbeulich@suse.com>
* i386-gen.c (operand_type_shorthands): New.
(opcode_modifiers): Replace Reg<N> with just Reg.
(set_bitfield_from_cpu_flag_init): Rename to
set_bitfield_from_shorthand. Drop value parameter. Process
operand_type_shorthands.
(set_bitfield): Adjust call accordingly.
* i386-opc.h (enum of operand types): Replace Reg<N> with just
Reg.
(union i386_operand_type): Replace reg<N> with just reg.
* i386-opc.tbl (extractps, pextrb, pextrw, pinsrb, pinsrw,
vextractps, vpextrb, vpextrw, vpinsrb, vpinsrw): Split into
separate register and memory forms.
* i386-reg.tbl (al): Drop Byte.
(ax): Drop Word.
(eax): Drop Dword.
(rax): Drop Qword.
* i386-init.h, i386-tbl.h: Re-generate.
--- a/gas/config/tc-i386-intel.c
+++ b/gas/config/tc-i386-intel.c
@@ -451,7 +451,7 @@ static int i386_intel_simplify (expressi
{
resolve_expression (scale);
if (scale->X_op != O_constant
- || intel_state.index->reg_type.bitfield.reg16)
+ || intel_state.index->reg_type.bitfield.word)
scale->X_add_number = 0;
intel_state.scale_factor *= scale->X_add_number;
}
@@ -897,8 +897,8 @@ i386_intel_operand (char *operand_string
mode we have to do this here. */
if (intel_state.base
&& intel_state.index
- && intel_state.base->reg_type.bitfield.reg16
- && intel_state.index->reg_type.bitfield.reg16
+ && intel_state.base->reg_type.bitfield.word
+ && intel_state.index->reg_type.bitfield.word
&& intel_state.base->reg_num >= 6
&& intel_state.index->reg_num < 6)
{
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -1775,10 +1775,7 @@ operand_type_check (i386_operand_type t,
switch (c)
{
case reg:
- return (t.bitfield.reg8
- || t.bitfield.reg16
- || t.bitfield.reg32
- || t.bitfield.reg64);
+ return t.bitfield.reg;
case imm:
return (t.bitfield.imm8
@@ -1867,10 +1864,12 @@ operand_size_match (const insn_template
/* Check memory and accumulator operand size. */
for (j = 0; j < i.operands; j++)
{
- if (t->operand_types[j].bitfield.anysize)
+ if (!i.types[j].bitfield.reg && t->operand_types[j].bitfield.anysize)
continue;
- if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
+ if ((t->operand_types[j].bitfield.reg
+ || t->operand_types[j].bitfield.acc)
+ && !match_reg_size (t, j))
{
match = 0;
break;
@@ -1898,7 +1897,8 @@ mismatch:
match = 1;
for (j = 0; j < 2; j++)
{
- if (t->operand_types[j].bitfield.acc
+ if ((t->operand_types[j].bitfield.reg
+ || t->operand_types[j].bitfield.acc)
&& !match_reg_size (t, j ? 0 : 1))
goto mismatch;
@@ -1940,14 +1940,11 @@ mismatch:
}
/* If given types g0 and g1 are registers they must be of the same type
- unless the expected operand type register overlap is null.
- Note that Acc in a template matches every size of reg. */
+ unless the expected operand type register overlap is null. */
static INLINE int
-operand_type_register_match (i386_operand_type m0,
- i386_operand_type g0,
+operand_type_register_match (i386_operand_type g0,
i386_operand_type t0,
- i386_operand_type m1,
i386_operand_type g1,
i386_operand_type t1)
{
@@ -1957,32 +1954,16 @@ operand_type_register_match (i386_operan
if (!operand_type_check (g1, reg))
return 1;
- if (g0.bitfield.reg8 == g1.bitfield.reg8
- && g0.bitfield.reg16 == g1.bitfield.reg16
- && g0.bitfield.reg32 == g1.bitfield.reg32
- && g0.bitfield.reg64 == g1.bitfield.reg64)
+ if (g0.bitfield.byte == g1.bitfield.byte
+ && g0.bitfield.word == g1.bitfield.word
+ && g0.bitfield.dword == g1.bitfield.dword
+ && g0.bitfield.qword == g1.bitfield.qword)
return 1;
- if (m0.bitfield.acc)
- {
- t0.bitfield.reg8 = 1;
- t0.bitfield.reg16 = 1;
- t0.bitfield.reg32 = 1;
- t0.bitfield.reg64 = 1;
- }
-
- if (m1.bitfield.acc)
- {
- t1.bitfield.reg8 = 1;
- t1.bitfield.reg16 = 1;
- t1.bitfield.reg32 = 1;
- t1.bitfield.reg64 = 1;
- }
-
- if (!(t0.bitfield.reg8 & t1.bitfield.reg8)
- && !(t0.bitfield.reg16 & t1.bitfield.reg16)
- && !(t0.bitfield.reg32 & t1.bitfield.reg32)
- && !(t0.bitfield.reg64 & t1.bitfield.reg64))
+ if (!(t0.bitfield.byte & t1.bitfield.byte)
+ && !(t0.bitfield.word & t1.bitfield.word)
+ && !(t0.bitfield.dword & t1.bitfield.dword)
+ && !(t0.bitfield.qword & t1.bitfield.qword))
return 1;
i.error = register_type_mismatch;
@@ -2821,10 +2802,7 @@ pi (char *line, i386_insn *x)
fprintf (stdout, " #%d: ", j + 1);
pt (x->types[j]);
fprintf (stdout, "\n");
- if (x->types[j].bitfield.reg8
- || x->types[j].bitfield.reg16
- || x->types[j].bitfield.reg32
- || x->types[j].bitfield.reg64
+ if (x->types[j].bitfield.reg
|| x->types[j].bitfield.regmmx
|| x->types[j].bitfield.regxmm
|| x->types[j].bitfield.regymm
@@ -3856,12 +3834,12 @@ md_assemble (char *line)
instruction already has a prefix, we need to convert old
registers to new ones. */
- if ((i.types[0].bitfield.reg8
+ if ((i.types[0].bitfield.reg && i.types[0].bitfield.byte
&& (i.op[0].regs->reg_flags & RegRex64) != 0)
- || (i.types[1].bitfield.reg8
+ || (i.types[1].bitfield.reg && i.types[1].bitfield.byte
&& (i.op[1].regs->reg_flags & RegRex64) != 0)
- || ((i.types[0].bitfield.reg8
- || i.types[1].bitfield.reg8)
+ || (((i.types[0].bitfield.reg && i.types[0].bitfield.byte)
+ || (i.types[1].bitfield.reg && i.types[1].bitfield.byte))
&& i.rex != 0))
{
int x;
@@ -3870,7 +3848,7 @@ md_assemble (char *line)
for (x = 0; x < 2; x++)
{
/* Look for 8 bit operand that uses old registers. */
- if (i.types[x].bitfield.reg8
+ if (i.types[x].bitfield.reg && i.types[x].bitfield.byte
&& (i.op[x].regs->reg_flags & RegRex64) == 0)
{
/* In case it is "hi" register, give up. */
@@ -4377,22 +4355,22 @@ optimize_imm (void)
but the following works for instructions with immediates.
In any case, we can't set i.suffix yet. */
for (op = i.operands; --op >= 0;)
- if (i.types[op].bitfield.reg8)
+ if (i.types[op].bitfield.reg && i.types[op].bitfield.byte)
{
guess_suffix = BYTE_MNEM_SUFFIX;
break;
}
- else if (i.types[op].bitfield.reg16)
+ else if (i.types[op].bitfield.reg && i.types[op].bitfield.word)
{
guess_suffix = WORD_MNEM_SUFFIX;
break;
}
- else if (i.types[op].bitfield.reg32)
+ else if (i.types[op].bitfield.reg && i.types[op].bitfield.dword)
{
guess_suffix = LONG_MNEM_SUFFIX;
break;
}
- else if (i.types[op].bitfield.reg64)
+ else if (i.types[op].bitfield.reg && i.types[op].bitfield.qword)
{
guess_suffix = QWORD_MNEM_SUFFIX;
break;
@@ -5084,9 +5062,9 @@ match_template (char mnem_suffix)
if (!operand_type_match (overlap0, i.types[0])
|| !operand_type_match (overlap1, i.types[1])
|| (check_register
- && !operand_type_register_match (overlap0, i.types[0],
+ && !operand_type_register_match (i.types[0],
operand_types[0],
- overlap1, i.types[1],
+ i.types[1],
operand_types[1])))
{
/* Check if other direction is valid ... */
@@ -5100,10 +5078,8 @@ check_reverse:
if (!operand_type_match (overlap0, i.types[0])
|| !operand_type_match (overlap1, i.types[1])
|| (check_register
- && !operand_type_register_match (overlap0,
- i.types[0],
+ && !operand_type_register_match (i.types[0],
operand_types[1],
- overlap1,
i.types[1],
operand_types[0])))
{
@@ -5144,10 +5120,8 @@ check_reverse:
{
case 5:
if (!operand_type_match (overlap4, i.types[4])
- || !operand_type_register_match (overlap3,
- i.types[3],
+ || !operand_type_register_match (i.types[3],
operand_types[3],
- overlap4,
i.types[4],
operand_types[4]))
continue;
@@ -5155,10 +5129,8 @@ check_reverse:
case 4:
if (!operand_type_match (overlap3, i.types[3])
|| (check_register
- && !operand_type_register_match (overlap2,
- i.types[2],
+ && !operand_type_register_match (i.types[2],
operand_types[2],
- overlap3,
i.types[3],
operand_types[3])))
continue;
@@ -5170,10 +5142,8 @@ check_reverse:
register consistency between operands 2 and 3. */
if (!operand_type_match (overlap2, i.types[2])
|| (check_register
- && !operand_type_register_match (overlap1,
- i.types[1],
+ && !operand_type_register_match (i.types[1],
operand_types[1],
- overlap2,
i.types[2],
operand_types[2])))
continue;
@@ -5381,16 +5351,16 @@ process_suffix (void)
type. */
if (i.tm.base_opcode == 0xf20f38f1)
{
- if (i.types[0].bitfield.reg16)
+ if (i.types[0].bitfield.reg && i.types[0].bitfield.word)
i.suffix = WORD_MNEM_SUFFIX;
- else if (i.types[0].bitfield.reg32)
+ else if (i.types[0].bitfield.reg && i.types[0].bitfield.dword)
i.suffix = LONG_MNEM_SUFFIX;
- else if (i.types[0].bitfield.reg64)
+ else if (i.types[0].bitfield.reg && i.types[0].bitfield.qword)
i.suffix = QWORD_MNEM_SUFFIX;
}
else if (i.tm.base_opcode == 0xf20f38f0)
{
- if (i.types[0].bitfield.reg8)
+ if (i.types[0].bitfield.reg && i.types[0].bitfield.byte)
i.suffix = BYTE_MNEM_SUFFIX;
}
@@ -5411,22 +5381,22 @@ process_suffix (void)
if (!i.tm.operand_types[op].bitfield.inoutportreg
&& !i.tm.operand_types[op].bitfield.shiftcount)
{
- if (i.types[op].bitfield.reg8)
+ if (i.types[op].bitfield.reg && i.types[op].bitfield.byte)
{
i.suffix = BYTE_MNEM_SUFFIX;
break;
}
- else if (i.types[op].bitfield.reg16)
+ if (i.types[op].bitfield.reg && i.types[op].bitfield.word)
{
i.suffix = WORD_MNEM_SUFFIX;
break;
}
- else if (i.types[op].bitfield.reg32)
+ if (i.types[op].bitfield.reg && i.types[op].bitfield.dword)
{
i.suffix = LONG_MNEM_SUFFIX;
break;
}
- else if (i.types[op].bitfield.reg64)
+ if (i.types[op].bitfield.reg && i.types[op].bitfield.qword)
{
i.suffix = QWORD_MNEM_SUFFIX;
break;
@@ -5583,9 +5553,9 @@ process_suffix (void)
/* The address size override prefix changes the size of the
first operand. */
if ((flag_code == CODE_32BIT
- && i.op->regs[0].reg_type.bitfield.reg16)
+ && i.op->regs[0].reg_type.bitfield.word)
|| (flag_code != CODE_32BIT
- && i.op->regs[0].reg_type.bitfield.reg32))
+ && i.op->regs[0].reg_type.bitfield.dword))
if (!add_prefix (ADDR_PREFIX_OPCODE))
return 0;
}
@@ -5642,10 +5612,14 @@ check_byte_reg (void)
for (op = i.operands; --op >= 0;)
{
+ /* Skip non-register operands. */
+ if (!i.types[op].bitfield.reg)
+ continue;
+
/* If this is an eight bit register, it's OK. If it's the 16 or
32 bit version of an eight bit register, we will just use the
low portion, and that's OK too. */
- if (i.types[op].bitfield.reg8)
+ if (i.types[op].bitfield.byte)
continue;
/* I/O port address operands are OK too. */
@@ -5656,9 +5630,9 @@ check_byte_reg (void)
if (i.tm.base_opcode == 0xf20f38f0)
continue;
- if ((i.types[op].bitfield.reg16
- || i.types[op].bitfield.reg32
- || i.types[op].bitfield.reg64)
+ if ((i.types[op].bitfield.word
+ || i.types[op].bitfield.dword
+ || i.types[op].bitfield.qword)
&& i.op[op].regs->reg_num < 4
/* Prohibit these changes in 64bit mode, since the lowering
would be more complicated. */
@@ -5668,7 +5642,7 @@ check_byte_reg (void)
if (!quiet_warnings)
as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
register_prefix,
- (i.op[op].regs + (i.types[op].bitfield.reg16
+ (i.op[op].regs + (i.types[op].bitfield.word
? REGNAM_AL - REGNAM_AX
: REGNAM_AL - REGNAM_EAX))->reg_name,
register_prefix,
@@ -5678,9 +5652,7 @@ check_byte_reg (void)
continue;
}
/* Any other register is bad. */
- if (i.types[op].bitfield.reg16
- || i.types[op].bitfield.reg32
- || i.types[op].bitfield.reg64
+ if (i.types[op].bitfield.reg
|| i.types[op].bitfield.regmmx
|| i.types[op].bitfield.regxmm
|| i.types[op].bitfield.regymm
@@ -5710,12 +5682,16 @@ check_long_reg (void)
int op;
for (op = i.operands; --op >= 0;)
+ /* Skip non-register operands. */
+ if (!i.types[op].bitfield.reg)
+ continue;
/* Reject eight bit registers, except where the template requires
them. (eg. movzb) */
- if (i.types[op].bitfield.reg8
- && (i.tm.operand_types[op].bitfield.reg16
- || i.tm.operand_types[op].bitfield.reg32
- || i.tm.operand_types[op].bitfield.acc))
+ else if (i.types[op].bitfield.byte
+ && (i.tm.operand_types[op].bitfield.reg
+ || i.tm.operand_types[op].bitfield.acc)
+ && (i.tm.operand_types[op].bitfield.word
+ || i.tm.operand_types[op].bitfield.dword))
{
as_bad (_("`%s%s' not allowed with `%s%c'"),
register_prefix,
@@ -5726,9 +5702,10 @@ check_long_reg (void)
}
/* Warn if the e prefix on a general reg is missing. */
else if ((!quiet_warnings || flag_code == CODE_64BIT)
- && i.types[op].bitfield.reg16
- && (i.tm.operand_types[op].bitfield.reg32
- || i.tm.operand_types[op].bitfield.acc))
+ && i.types[op].bitfield.word
+ && (i.tm.operand_types[op].bitfield.reg
+ || i.tm.operand_types[op].bitfield.acc)
+ && i.tm.operand_types[op].bitfield.dword)
{
/* Prohibit these changes in the 64bit mode, since the
lowering is more complicated. */
@@ -5747,9 +5724,10 @@ check_long_reg (void)
#endif
}
/* Warn if the r prefix on a general reg is present. */
- else if (i.types[op].bitfield.reg64
- && (i.tm.operand_types[op].bitfield.reg32
- || i.tm.operand_types[op].bitfield.acc))
+ else if (i.types[op].bitfield.qword
+ && (i.tm.operand_types[op].bitfield.reg
+ || i.tm.operand_types[op].bitfield.acc)
+ && i.tm.operand_types[op].bitfield.dword)
{
if (intel_syntax
&& i.tm.opcode_modifier.toqword
@@ -5775,12 +5753,16 @@ check_qword_reg (void)
int op;
for (op = i.operands; --op >= 0; )
+ /* Skip non-register operands. */
+ if (!i.types[op].bitfield.reg)
+ continue;
/* Reject eight bit registers, except where the template requires
them. (eg. movzb) */
- if (i.types[op].bitfield.reg8
- && (i.tm.operand_types[op].bitfield.reg16
- || i.tm.operand_types[op].bitfield.reg32
- || i.tm.operand_types[op].bitfield.acc))
+ else if (i.types[op].bitfield.byte
+ && (i.tm.operand_types[op].bitfield.reg
+ || i.tm.operand_types[op].bitfield.acc)
+ && (i.tm.operand_types[op].bitfield.word
+ || i.tm.operand_types[op].bitfield.dword))
{
as_bad (_("`%s%s' not allowed with `%s%c'"),
register_prefix,
@@ -5790,10 +5772,11 @@ check_qword_reg (void)
return 0;
}
/* Warn if the r prefix on a general reg is missing. */
- else if ((i.types[op].bitfield.reg16
- || i.types[op].bitfield.reg32)
- && (i.tm.operand_types[op].bitfield.reg64
- || i.tm.operand_types[op].bitfield.acc))
+ else if ((i.types[op].bitfield.word
+ || i.types[op].bitfield.dword)
+ && (i.tm.operand_types[op].bitfield.reg
+ || i.tm.operand_types[op].bitfield.acc)
+ && i.tm.operand_types[op].bitfield.qword)
{
/* Prohibit these changes in the 64bit mode, since the
lowering is more complicated. */
@@ -5820,12 +5803,16 @@ check_word_reg (void)
{
int op;
for (op = i.operands; --op >= 0;)
+ /* Skip non-register operands. */
+ if (!i.types[op].bitfield.reg)
+ continue;
/* Reject eight bit registers, except where the template requires
them. (eg. movzb) */
- if (i.types[op].bitfield.reg8
- && (i.tm.operand_types[op].bitfield.reg16
- || i.tm.operand_types[op].bitfield.reg32
- || i.tm.operand_types[op].bitfield.acc))
+ else if (i.types[op].bitfield.byte
+ && (i.tm.operand_types[op].bitfield.reg
+ || i.tm.operand_types[op].bitfield.acc)
+ && (i.tm.operand_types[op].bitfield.word
+ || i.tm.operand_types[op].bitfield.dword))
{
as_bad (_("`%s%s' not allowed with `%s%c'"),
register_prefix,
@@ -5836,10 +5823,11 @@ check_word_reg (void)
}
/* Warn if the e or r prefix on a general reg is present. */
else if ((!quiet_warnings || flag_code == CODE_64BIT)
- && (i.types[op].bitfield.reg32
- || i.types[op].bitfield.reg64)
- && (i.tm.operand_types[op].bitfield.reg16
- || i.tm.operand_types[op].bitfield.acc))
+ && (i.types[op].bitfield.dword
+ || i.types[op].bitfield.qword)
+ && (i.tm.operand_types[op].bitfield.reg
+ || i.tm.operand_types[op].bitfield.acc)
+ && i.tm.operand_types[op].bitfield.word)
{
/* Prohibit these changes in the 64bit mode, since the
lowering is more complicated. */
@@ -6458,8 +6446,8 @@ build_modrm_byte (void)
op = i.tm.operand_types[vvvv];
op.bitfield.regmem = 0;
if ((dest + 1) >= i.operands
- || (!op.bitfield.reg32
- && !op.bitfield.reg64
+ || ((!op.bitfield.reg
+ || (!op.bitfield.dword && !op.bitfield.qword))
&& !operand_type_equal (&op, ®xmm)
&& !operand_type_equal (&op, ®ymm)
&& !operand_type_equal (&op, ®zmm)
@@ -6639,7 +6627,7 @@ build_modrm_byte (void)
if (! i.disp_operands)
fake_zero_displacement = 1;
}
- else if (i.base_reg->reg_type.bitfield.reg16)
+ else if (i.base_reg->reg_type.bitfield.word)
{
gas_assert (!i.tm.opcode_modifier.vecsib);
switch (i.base_reg->reg_num)
@@ -6819,10 +6807,7 @@ build_modrm_byte (void)
unsigned int vex_reg = ~0;
for (op = 0; op < i.operands; op++)
- if (i.types[op].bitfield.reg8
- || i.types[op].bitfield.reg16
- || i.types[op].bitfield.reg32
- || i.types[op].bitfield.reg64
+ if (i.types[op].bitfield.reg
|| i.types[op].bitfield.regmmx
|| i.types[op].bitfield.regxmm
|| i.types[op].bitfield.regymm
@@ -6892,8 +6877,8 @@ build_modrm_byte (void)
{
i386_operand_type *type = &i.tm.operand_types[vex_reg];
- if (type->bitfield.reg32 != 1
- && type->bitfield.reg64 != 1
+ if ((!type->bitfield.reg
+ || (!type->bitfield.dword && !type->bitfield.qword))
&& !operand_type_equal (type, ®xmm)
&& !operand_type_equal (type, ®ymm)
&& !operand_type_equal (type, ®zmm)
@@ -7351,7 +7336,7 @@ check_prefix:
==> need second modrm byte. */
if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
&& i.rm.mode != 3
- && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
+ && !(i.base_reg && i.base_reg->reg_type.bitfield.word))
FRAG_APPEND_1_CHAR ((i.sib.base << 0
| i.sib.index << 3
| i.sib.scale << 6));
@@ -8620,10 +8605,10 @@ i386_addressing_mode (void)
{
if (addr_reg->reg_num == RegEip
|| addr_reg->reg_num == RegEiz
- || addr_reg->reg_type.bitfield.reg32)
+ || addr_reg->reg_type.bitfield.dword)
addr_mode = CODE_32BIT;
else if (flag_code != CODE_64BIT
- && addr_reg->reg_type.bitfield.reg16)
+ && addr_reg->reg_type.bitfield.word)
addr_mode = CODE_16BIT;
if (addr_mode != flag_code)
@@ -8702,10 +8687,10 @@ i386_index_check (const char *operand_st
if (i.mem_operands
&& i.base_reg
&& !((addr_mode == CODE_64BIT
- && i.base_reg->reg_type.bitfield.reg64)
+ && i.base_reg->reg_type.bitfield.qword)
|| (addr_mode == CODE_32BIT
- ? i.base_reg->reg_type.bitfield.reg32
- : i.base_reg->reg_type.bitfield.reg16)))
+ ? i.base_reg->reg_type.bitfield.dword
+ : i.base_reg->reg_type.bitfield.word)))
goto bad_address;
as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
@@ -8731,8 +8716,8 @@ bad_address:
/* 32-bit/64-bit checks. */
if ((i.base_reg
&& (addr_mode == CODE_64BIT
- ? !i.base_reg->reg_type.bitfield.reg64
- : !i.base_reg->reg_type.bitfield.reg32)
+ ? !i.base_reg->reg_type.bitfield.qword
+ : !i.base_reg->reg_type.bitfield.dword)
&& (i.index_reg
|| (i.base_reg->reg_num
!= (addr_mode == CODE_64BIT ? RegRip : RegEip))))
@@ -8741,9 +8726,9 @@ bad_address:
&& !i.index_reg->reg_type.bitfield.regymm
&& !i.index_reg->reg_type.bitfield.regzmm
&& ((addr_mode == CODE_64BIT
- ? !(i.index_reg->reg_type.bitfield.reg64
+ ? !(i.index_reg->reg_type.bitfield.qword
|| i.index_reg->reg_num == RegRiz)
- : !(i.index_reg->reg_type.bitfield.reg32
+ : !(i.index_reg->reg_type.bitfield.dword
|| i.index_reg->reg_num == RegEiz))
|| !i.index_reg->reg_type.bitfield.baseindex)))
goto bad_address;
@@ -8769,10 +8754,10 @@ bad_address:
{
/* 16-bit checks. */
if ((i.base_reg
- && (!i.base_reg->reg_type.bitfield.reg16
+ && (!i.base_reg->reg_type.bitfield.word
|| !i.base_reg->reg_type.bitfield.baseindex))
|| (i.index_reg
- && (!i.index_reg->reg_type.bitfield.reg16
+ && (!i.index_reg->reg_type.bitfield.word
|| !i.index_reg->reg_type.bitfield.baseindex
|| !(i.base_reg
&& i.base_reg->reg_num < 6
@@ -9775,7 +9760,7 @@ parse_real_register (char *reg_string, c
if (operand_type_all_zero (&r->reg_type))
return (const reg_entry *) NULL;
- if ((r->reg_type.bitfield.reg32
+ if ((r->reg_type.bitfield.dword
|| r->reg_type.bitfield.sreg3
|| r->reg_type.bitfield.control
|| r->reg_type.bitfield.debug
@@ -9824,7 +9809,7 @@ parse_real_register (char *reg_string, c
}
if (((r->reg_flags & (RegRex64 | RegRex))
- || r->reg_type.bitfield.reg64)
+ || r->reg_type.bitfield.qword)
&& (!cpu_arch_flags.bitfield.cpulm
|| !operand_type_equal (&r->reg_type, &control))
&& flag_code != CODE_64BIT)
--- a/opcodes/i386-gen.c
+++ b/opcodes/i386-gen.c
@@ -335,6 +335,14 @@ static initializer cpu_flag_init[] =
"CpuAVX512_BITALG" },
};
+static const initializer operand_type_shorthands[] =
+{
+ { "Reg8", "Reg|Byte" },
+ { "Reg16", "Reg|Word" },
+ { "Reg32", "Reg|Dword" },
+ { "Reg64", "Reg|Qword" },
+};
+
static initializer operand_type_init[] =
{
{ "OPERAND_TYPE_NONE",
@@ -631,10 +639,7 @@ static bitfield opcode_modifiers[] =
static bitfield operand_types[] =
{
- BITFIELD (Reg8),
- BITFIELD (Reg16),
- BITFIELD (Reg32),
- BITFIELD (Reg64),
+ BITFIELD (Reg),
BITFIELD (FloatReg),
BITFIELD (RegMMX),
BITFIELD (RegXMM),
@@ -789,9 +794,8 @@ next_field (char *str, char sep, char **
static void set_bitfield (char *, bitfield *, int, unsigned int, int);
static int
-set_bitfield_from_cpu_flag_init (char *f, bitfield *array,
- int value, unsigned int size,
- int lineno)
+set_bitfield_from_shorthand (char *f, bitfield *array, unsigned int size,
+ int lineno)
{
char *str, *next, *last;
unsigned int i;
@@ -812,6 +816,22 @@ set_bitfield_from_cpu_flag_init (char *f
return 0;
}
+ for (i = 0; i < ARRAY_SIZE (operand_type_shorthands); i++)
+ if (strcmp (operand_type_shorthands[i].name, f) == 0)
+ {
+ /* Turn on selective bits. */
+ char *init = xstrdup (operand_type_shorthands[i].init);
+ last = init + strlen (init);
+ for (next = init; next && next < last; )
+ {
+ str = next_field (next, '|', &next, last);
+ if (str)
+ set_bitfield (str, array, 1, size, lineno);
+ }
+ free (init);
+ return 0;
+ }
+
return -1;
}
@@ -862,8 +882,8 @@ set_bitfield (char *f, bitfield *array,
}
}
- /* Handle CPU_XXX_FLAGS. */
- if (!set_bitfield_from_cpu_flag_init (f, array, value, size, lineno))
+ /* Handle shorthands. */
+ if (value == 1 && !set_bitfield_from_shorthand (f, array, size, lineno))
return;
if (lineno != -1)
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -685,14 +685,8 @@ typedef struct i386_opcode_modifier
enum
{
- /* 8bit register */
- Reg8 = 0,
- /* 16bit register */
- Reg16,
- /* 32bit register */
- Reg32,
- /* 64bit register */
- Reg64,
+ /* Register (qualified by Byte, Word, etc) */
+ Reg = 0,
/* Floating pointer stack register */
FloatReg,
/* MMX register */
@@ -814,10 +808,7 @@ typedef union i386_operand_type
{
struct
{
- unsigned int reg8:1;
- unsigned int reg16:1;
- unsigned int reg32:1;
- unsigned int reg64:1;
+ unsigned int reg:1;
unsigned int floatreg:1;
unsigned int regmmx:1;
unsigned int regxmm:1;
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -1269,13 +1269,18 @@ pavgw, 2, 0xfe3, None, 2, CpuSSE|Cpu3dno
pavgw, 2, 0x66e3, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
pavgw, 2, 0x660fe3, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
pextrw, 3, 0x66c5, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64|SSE2AVX, { Imm8, RegXMM, Reg32|Reg64 }
-pextrw, 3, 0x6615, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|SSE2AVX, { Imm8, RegXMM, Reg32|Reg64|Word|Unspecified|BaseIndex }
+pextrw, 3, 0x6615, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|SSE2AVX, { Imm8, RegXMM, Reg32|Reg64|RegMem }
+pextrw, 3, 0x6615, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, RegXMM, Word|Unspecified|BaseIndex }
pextrw, 3, 0x660fc5, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { Imm8, RegXMM, Reg32|Reg64 }
-pextrw, 3, 0x660f3a15, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Imm8, RegXMM, Reg32|Reg64|Word|Unspecified|BaseIndex }
+pextrw, 3, 0x660f3a15, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Imm8, RegXMM, Reg32|Reg64|RegMem }
+pextrw, 3, 0x660f3a15, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Word|Unspecified|BaseIndex }
pextrw, 3, 0xfc5, None, 2, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64|NoAVX, { Imm8, RegMMX, Reg32|Reg64 }
-pinsrw, 3, 0x66c4, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64|SSE2AVX, { Imm8, Reg32|Reg64|Word|Unspecified|BaseIndex, RegXMM }
-pinsrw, 3, 0x660fc4, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { Imm8, Reg32|Reg64|Word|Unspecified|BaseIndex, RegXMM }
-pinsrw, 3, 0xfc4, None, 2, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64|NoAVX, { Imm8, Reg32|Reg64|Word|Unspecified|BaseIndex, RegMMX }
+pinsrw, 3, 0x66c4, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64|SSE2AVX, { Imm8, Reg32|Reg64, RegXMM }
+pinsrw, 3, 0x66c4, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|SSE2AVX, { Imm8, Word|Unspecified|BaseIndex, RegXMM }
+pinsrw, 3, 0x660fc4, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { Imm8, Reg32|Reg64, RegXMM }
+pinsrw, 3, 0x660fc4, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Imm8, Word|Unspecified|BaseIndex, RegXMM }
+pinsrw, 3, 0xfc4, None, 2, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64|NoAVX, { Imm8, Reg32|Reg64, RegMMX }
+pinsrw, 3, 0xfc4, None, 2, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoAVX, { Imm8, Word|Unspecified|BaseIndex, RegMMX }
pmaxsw, 2, 0x66ee, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
pmaxsw, 2, 0x660fee, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
pmaxsw, 2, 0xfee, None, 2, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
@@ -1656,8 +1661,10 @@ dppd, 3, 0x6641, None, 1, CpuAVX, Modrm|
dppd, 3, 0x660f3a41, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
dpps, 3, 0x6640, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
dpps, 3, 0x660f3a40, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
-extractps, 3, 0x6617, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|SSE2AVX, { Imm8, RegXMM, Reg32|Reg64|Dword|Unspecified|BaseIndex }
-extractps, 3, 0x660f3a17, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Imm8, RegXMM, Reg32|Reg64|Dword|Unspecified|BaseIndex }
+extractps, 3, 0x6617, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, RegXMM, Reg32|Dword|Unspecified|BaseIndex }
+extractps, 3, 0x6617, None, 1, CpuAVX|Cpu64, Modrm|Vex|VexOpcode=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|SSE2AVX, { Imm8, RegXMM, Reg64|RegMem }
+extractps, 3, 0x660f3a17, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg32|Dword|Unspecified|BaseIndex }
+extractps, 3, 0x660f3a17, None, 3, CpuSSE4_1|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Imm8, RegXMM, Reg64|RegMem }
insertps, 3, 0x6621, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
insertps, 3, 0x660f3a21, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
movntdqa, 2, 0x662a, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex, RegXMM }
@@ -1674,16 +1681,20 @@ pblendw, 3, 0x660e, None, 1, CpuAVX, Mod
pblendw, 3, 0x660f3a0e, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
pcmpeqq, 2, 0x6629, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
pcmpeqq, 2, 0x660f3829, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
-pextrb, 3, 0x6614, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|SSE2AVX, { Imm8, RegXMM, Reg32|Reg64|Byte|Unspecified|BaseIndex }
-pextrb, 3, 0x660f3a14, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Imm8, RegXMM, Reg32|Reg64|Byte|Unspecified|BaseIndex }
+pextrb, 3, 0x6614, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|SSE2AVX, { Imm8, RegXMM, Reg32|Reg64|RegMem }
+pextrb, 3, 0x6614, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, RegXMM, Byte|Unspecified|BaseIndex }
+pextrb, 3, 0x660f3a14, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Imm8, RegXMM, Reg32|Reg64|RegMem }
+pextrb, 3, 0x660f3a14, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Byte|Unspecified|BaseIndex }
pextrd, 3, 0x6616, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, RegXMM, Reg32|Dword|Unspecified|BaseIndex }
pextrd, 3, 0x660f3a16, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg32|Dword|Unspecified|BaseIndex }
pextrq, 3, 0x6616, None, 1, CpuAVX|Cpu64, Modrm|Vex|VexOpcode=2|Size64|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, RegXMM, Reg64|Qword|Unspecified|BaseIndex }
pextrq, 3, 0x660f3a16, None, 3, CpuSSE4_1|Cpu64, Modrm|Size64|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg64|Qword|Unspecified|BaseIndex }
phminposuw, 2, 0x6641, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
phminposuw, 2, 0x660f3841, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
-pinsrb, 3, 0x6620, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|SSE2AVX, { Imm8, Reg32|Reg64|Byte|Unspecified|BaseIndex, RegXMM }
-pinsrb, 3, 0x660f3a20, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Imm8, Reg32|Reg64|Byte|Unspecified|BaseIndex, RegXMM }
+pinsrb, 3, 0x6620, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|SSE2AVX, { Imm8, Reg32|Reg64, RegXMM }
+pinsrb, 3, 0x6620, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, Byte|Unspecified|BaseIndex, RegXMM }
+pinsrb, 3, 0x660f3a20, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Imm8, Reg32|Reg64, RegXMM }
+pinsrb, 3, 0x660f3a20, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Byte|Unspecified|BaseIndex, RegXMM }
pinsrd, 3, 0x6622, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexVVVV=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, Reg32|Dword|Unspecified|BaseIndex, RegXMM }
pinsrd, 3, 0x660f3a22, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Reg32|Dword|Unspecified|BaseIndex, RegXMM }
pinsrq, 3, 0x6622, None, 1, CpuAVX|Cpu64, Modrm|Vex|VexOpcode=2|Size64|VexVVVV=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, Reg64|Qword|Unspecified|BaseIndex, RegXMM }
@@ -2103,7 +2114,8 @@ vdppd, 4, 0x6641, None, 1, CpuAVX, Modrm
vdpps, 4, 0x6640, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vdpps, 4, 0x6640, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=2|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Ymmword|Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
vextractf128, 3, 0x6619, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM, Xmmword|Unspecified|BaseIndex|RegXMM }
-vextractps, 3, 0x6617, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Imm8, RegXMM, Reg32|Reg64|Dword|Unspecified|BaseIndex }
+vextractps, 3, 0x6617, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg32|Dword|Unspecified|BaseIndex }
+vextractps, 3, 0x6617, None, 1, CpuAVX|Cpu64, Modrm|Vex|VexOpcode=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Imm8, RegXMM, Reg64|RegMem }
vhaddpd, 3, 0x667c, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vhaddpd, 3, 0x667c, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
vhaddps, 3, 0xf27c, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
@@ -2266,11 +2278,13 @@ vpermilps, 3, 0x660c, None, 1, CpuAVX, M
vpermilps, 3, 0x660c, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
vpermilps, 3, 0x6604, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
vpermilps, 3, 0x6604, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Ymmword|Unspecified|BaseIndex|RegYMM, RegYMM }
-vpextrb, 3, 0x6614, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Imm8, RegXMM, Reg32|Reg64|Byte|Unspecified|BaseIndex }
+vpextrb, 3, 0x6614, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Imm8, RegXMM, Reg32|Reg64|RegMem }
+vpextrb, 3, 0x6614, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Byte|Unspecified|BaseIndex }
vpextrd, 3, 0x6616, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg32|Dword|Unspecified|BaseIndex }
vpextrq, 3, 0x6616, None, 1, CpuAVX|Cpu64, Modrm|Vex|VexOpcode=2|Size64|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg64|Qword|Unspecified|BaseIndex }
vpextrw, 3, 0x66c5, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { Imm8, RegXMM, Reg32|Reg64 }
-vpextrw, 3, 0x6615, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Imm8, RegXMM, Reg32|Reg64|Word|Unspecified|BaseIndex }
+vpextrw, 3, 0x6615, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Imm8, RegXMM, Reg32|Reg64|RegMem }
+vpextrw, 3, 0x6615, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Word|Unspecified|BaseIndex }
vphaddd, 3, 0x6602, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vphaddsw, 3, 0x6603, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vphaddw, 3, 0x6601, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
@@ -2278,10 +2292,12 @@ vphminposuw, 2, 0x6641, None, 1, CpuAVX,
vphsubd, 3, 0x6606, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vphsubsw, 3, 0x6607, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vphsubw, 3, 0x6605, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
-vpinsrb, 4, 0x6620, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Imm8, Reg32|Reg64|Byte|Unspecified|BaseIndex, RegXMM, RegXMM }
+vpinsrb, 4, 0x6620, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Imm8, Reg32|Reg64, RegXMM, RegXMM }
+vpinsrb, 4, 0x6620, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Byte|Unspecified|BaseIndex, RegXMM, RegXMM }
vpinsrd, 4, 0x6622, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexVVVV=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Reg32|Dword|Unspecified|BaseIndex, RegXMM, RegXMM }
vpinsrq, 4, 0x6622, None, 1, CpuAVX|Cpu64, Modrm|Vex|VexOpcode=2|Size64|VexVVVV=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Reg64|Qword|Unspecified|BaseIndex, RegXMM, RegXMM }
-vpinsrw, 4, 0x66c4, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { Imm8, Reg32|Reg64|Word|Unspecified|BaseIndex, RegXMM, RegXMM }
+vpinsrw, 4, 0x66c4, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { Imm8, Reg32|Reg64, RegXMM, RegXMM }
+vpinsrw, 4, 0x66c4, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Imm8, Word|Unspecified|BaseIndex, RegXMM, RegXMM }
vpmaddubsw, 3, 0x6604, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vpmaddwd, 3, 0x66f5, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vpmaxsb, 3, 0x663c, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
@@ -3779,7 +3795,8 @@ vextractf64x4, 3, 0x661B, None, 1, CpuAV
vextracti64x4, 3, 0x663B, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|VexOpcode=2|VexW=2|VecESize=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegZMM, RegYMM|RegMem }
vextracti64x4, 3, 0x663B, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=2|VexOpcode=2|VexW=2|VecESize=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegZMM, YMMword|Unspecified|BaseIndex }
-vextractps, 3, 0x6617, None, 1, CpuAVX512F, Modrm|EVex=4|VexOpcode=2|Disp8MemShift=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg64|Reg32|Dword|Unspecified|BaseIndex }
+vextractps, 3, 0x6617, None, 1, CpuAVX512F, Modrm|EVex=4|VexOpcode=2|Disp8MemShift=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg32|Dword|Unspecified|BaseIndex }
+vextractps, 3, 0x6617, None, 1, CpuAVX512F|Cpu64, Modrm|EVex=4|VexOpcode=2|Disp8MemShift=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg64|RegMem }
vfixupimmpd, 4, 0x6654, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|VexOpcode=2|VexVVVV=1|VexW=2|VecESize=1|Broadcast=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM }
vfixupimmpd, 5, 0x6654, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|VexOpcode=2|VexVVVV=1|VexW=2|VecESize=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, Imm8, RegZMM, RegZMM, RegZMM }
@@ -5708,12 +5725,16 @@ vpsrldq, 3, 0x6673, 3, 1, CpuAVX512BW|Cp
vpsrldq, 3, 0x6673, 3, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|VexOpcode=0|VexVVVV=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, YMMword|Unspecified|BaseIndex, RegYMM }
vpextrw, 3, 0x66C5, None, 1, CpuAVX512BW, Modrm|EVex=4|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg32|Reg64 }
-vpinsrw, 4, 0x66C4, None, 1, CpuAVX512BW, Modrm|EVex=4|VexOpcode=0|VexVVVV=1|Disp8MemShift=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Reg32|Reg64|Word|Unspecified|BaseIndex, RegXMM, RegXMM }
+vpinsrw, 4, 0x66C4, None, 1, CpuAVX512BW, Modrm|EVex=4|VexOpcode=0|VexVVVV=1|Disp8MemShift=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Reg32|Reg64, RegXMM, RegXMM }
+vpinsrw, 4, 0x66C4, None, 1, CpuAVX512BW, Modrm|EVex=4|VexOpcode=0|VexVVVV=1|Disp8MemShift=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Word|Unspecified|BaseIndex, RegXMM, RegXMM }
-vpextrb, 3, 0x6614, None, 1, CpuAVX512BW, Modrm|EVex=4|VexOpcode=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg32|Reg64|Byte|Unspecified|BaseIndex }
-vpinsrb, 4, 0x6620, None, 1, CpuAVX512BW, Modrm|EVex=4|VexOpcode=2|VexVVVV=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Reg32|Reg64|Byte|Unspecified|BaseIndex, RegXMM, RegXMM }
+vpextrb, 3, 0x6614, None, 1, CpuAVX512BW, Modrm|EVex=4|VexOpcode=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg32|Reg64|RegMem }
+vpextrb, 3, 0x6614, None, 1, CpuAVX512BW, Modrm|EVex=4|VexOpcode=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Byte|Unspecified|BaseIndex }
+vpinsrb, 4, 0x6620, None, 1, CpuAVX512BW, Modrm|EVex=4|VexOpcode=2|VexVVVV=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Reg32|Reg64, RegXMM, RegXMM }
+vpinsrb, 4, 0x6620, None, 1, CpuAVX512BW, Modrm|EVex=4|VexOpcode=2|VexVVVV=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Byte|Unspecified|BaseIndex, RegXMM, RegXMM }
-vpextrw, 3, 0x6615, None, 1, CpuAVX512BW, Modrm|EVex=4|VexOpcode=2|Disp8MemShift=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg32|Reg64|Word|Unspecified|BaseIndex }
+vpextrw, 3, 0x6615, None, 1, CpuAVX512BW, Modrm|EVex=4|VexOpcode=2|Disp8MemShift=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg32|Reg64|RegMem }
+vpextrw, 3, 0x6615, None, 1, CpuAVX512BW, Modrm|EVex=4|VexOpcode=2|Disp8MemShift=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Word|Unspecified|BaseIndex }
vpmaddwd, 3, 0x66F5, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM }
vpmaddwd, 3, 0x66F5, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex, RegXMM, RegXMM }
--- a/opcodes/i386-reg.tbl
+++ b/opcodes/i386-reg.tbl
@@ -21,7 +21,7 @@
// Make %st first as we test for it.
st, FloatReg|FloatAcc, 0, 0, 11, 33
// 8 bit regs
-al, Reg8|Acc|Byte, 0, 0, Dw2Inval, Dw2Inval
+al, Reg8|Acc, 0, 0, Dw2Inval, Dw2Inval
cl, Reg8|ShiftCount, 0, 1, Dw2Inval, Dw2Inval
dl, Reg8, 0, 2, Dw2Inval, Dw2Inval
bl, Reg8, 0, 3, Dw2Inval, Dw2Inval
@@ -46,7 +46,7 @@ r13b, Reg8, RegRex|RegRex64, 5, Dw2Inval
r14b, Reg8, RegRex|RegRex64, 6, Dw2Inval, Dw2Inval
r15b, Reg8, RegRex|RegRex64, 7, Dw2Inval, Dw2Inval
// 16 bit regs
-ax, Reg16|Acc|Word, 0, 0, Dw2Inval, Dw2Inval
+ax, Reg16|Acc, 0, 0, Dw2Inval, Dw2Inval
cx, Reg16, 0, 1, Dw2Inval, Dw2Inval
dx, Reg16|InOutPortReg, 0, 2, Dw2Inval, Dw2Inval
bx, Reg16|BaseIndex, 0, 3, Dw2Inval, Dw2Inval
@@ -63,7 +63,7 @@ r13w, Reg16, RegRex, 5, Dw2Inval, Dw2Inv
r14w, Reg16, RegRex, 6, Dw2Inval, Dw2Inval
r15w, Reg16, RegRex, 7, Dw2Inval, Dw2Inval
// 32 bit regs
-eax, Reg32|BaseIndex|Acc|Dword, 0, 0, 0, Dw2Inval
+eax, Reg32|BaseIndex|Acc, 0, 0, 0, Dw2Inval
ecx, Reg32|BaseIndex, 0, 1, 1, Dw2Inval
edx, Reg32|BaseIndex, 0, 2, 2, Dw2Inval
ebx, Reg32|BaseIndex, 0, 3, 3, Dw2Inval
@@ -79,7 +79,7 @@ r12d, Reg32|BaseIndex, RegRex, 4, Dw2Inv
r13d, Reg32|BaseIndex, RegRex, 5, Dw2Inval, Dw2Inval
r14d, Reg32|BaseIndex, RegRex, 6, Dw2Inval, Dw2Inval
r15d, Reg32|BaseIndex, RegRex, 7, Dw2Inval, Dw2Inval
-rax, Reg64|BaseIndex|Acc|Qword, 0, 0, Dw2Inval, 0
+rax, Reg64|BaseIndex|Acc, 0, 0, Dw2Inval, 0
rcx, Reg64|BaseIndex, 0, 1, Dw2Inval, 2
rdx, Reg64|BaseIndex, 0, 2, Dw2Inval, 1
rbx, Reg64|BaseIndex, 0, 3, Dw2Inval, 3