Re: [gold patch] PR 22969: Add support for R_AARCH64_TLSLE_LDST8_TPREL_LO12, etc.

[Cary Coutant <ccoutant at gmail dot com>]

Thanks for the testing! I've applied the patch.

-cary

On Wed, Mar 28, 2018 at 8:18 AM, Renlin Li <renlin.li@foss.arm.com> wrote:
> Hi Cary,
>
> I applied your patch and compared the results of test cases in my ld linker
> patches.
> The results are identical.
>
> Renlin
>
>
> On 28/03/18 10:58, Peter Smith wrote:
>>
>> Hello Cary,
>>
>> The patch looks correct to me, I'm not a binutils maintainer so I
>> don't know what is needed for approval, I think Renlin Li is looking
>> into bfd so he might be another good person to check this out.
>>
>> I've checked it against the test case which can be assembled with
>> clang --target=aarch64-linux-gnu tls.s -c
>>
>>          .text
>>          .globl _start
>>          .type _start, %function
>> _start:  mrs x8, TPIDR_EL0
>>
>>          add x8, x8, :tprel_hi12:var0
>>          ldr x0, [x8, :tprel_lo12_nc:var0]
>>
>>          add x8, x8, :tprel_hi12:var1
>>          ldr w0, [x8, :tprel_lo12_nc:var1]
>>
>>          add x8, x8, :tprel_hi12:var2
>>          ldrh w0, [x8, :tprel_lo12_nc:var2]
>>
>>          add x8, x8, :tprel_hi12:var3
>>          ldrb w0, [x8, :tprel_lo12_nc:var3]
>>
>>          .globl var0
>>          .globl var1
>>          .globl var2
>>          .globl var3
>>          .type   var0,@object
>> .type var1,@object
>> .type var2,@object
>> .type var3,@object
>>
>> .section .tbss,"awT",@nobits
>> .p2align 2
>>          .space 1024 * 3
>> var0:
>> .quad 0
>> .size var1, 8
>>          .space 1024 * 3
>> var1:
>> .word 0
>> .size var1, 4
>>          .space 1024 * 3
>> var2:
>> .hword 0
>> .size var2, 2
>>          .space 1024 * 3
>> var3:
>> .byte 0
>> .size var3, 1
>>
>>
>>
>> On 28 March 2018 at 02:54, Cary Coutant <ccoutant@gmail.com> wrote:
>>>>
>>>> Can you please look over this patch and give it a test? Let me know if
>>>> it's OK to check in.
>>>>
>>>> 2018-03-27  Cary Coutant  <ccoutant@gmail.com>
>>>>
>>>> gold/
>>>>          PR gold/22969
>>>>          * aarch64-reloc.def: Add TLSLE_LDST* relocations.
>>>>          * aarch64.cc (Target_aarch64::optimize_tls_reloc): Likewise.
>>>>          (Target_aarch64::Scan::local): Likewise.
>>>>          (Target_aarch64::Scan::global): Likewise.
>>>>          (Target_aarch64::Relocate::relocate): Likewise.
>>>>          (Target_aarch64::Relocate::relocate_tls): Likewise.
>>>
>>>
>>> Oops, one more piece to the patch:
>>>
>>> elfcpp/
>>>          PR gold/22969
>>>          * aarch64.h: Fix spelling of
>>> R_AARCH64_TLSLE_LDST16_TPREL_LO12_NC.
>>>
>>> diff --git a/elfcpp/aarch64.h b/elfcpp/aarch64.h
>>> index 935a4d70f4..eb1ce6ae79 100644
>>> --- a/elfcpp/aarch64.h
>>> +++ b/elfcpp/aarch64.h
>>> @@ -146,7 +146,7 @@ enum
>>>     R_AARCH64_TLSLE_LDST8_TPREL_LO12 = 552,      // TPREL(S+A)
>>>     R_AARCH64_TLSLE_LDST8_TPREL_LO12_NC = 553,   // TPREL(S+A)
>>>     R_AARCH64_TLSLE_LDST16_TPREL_LO12 = 554,     // TPREL(S+A)
>>> -  R_AARCH64_TLSLE_LSDT16_TPREL_LO12_NC = 555,  // TPREL(S+A)
>>> +  R_AARCH64_TLSLE_LDST16_TPREL_LO12_NC = 555,  // TPREL(S+A)
>>>     R_AARCH64_TLSLE_LDST32_TPREL_LO12 = 556,     // TPREL(S+A)
>>>     R_AARCH64_TLSLE_LDST32_TPREL_LO12_NC = 557,  // TPREL(S+A)
>>>     R_AARCH64_TLSLE_LDST64_TPREL_LO12 = 558,     // TPREL(S+A)
>>>
>>> -cary