This is the mail archive of the
cgen@sources.redhat.com
mailing list for the CGEN project.
How to handle MIPS-like general register 0?
- To: Greg McGary <greg at mcgary dot org>
- Subject: How to handle MIPS-like general register 0?
- From: Doug Evans <dje at transmeta dot com>
- Date: Thu, 18 Jan 2001 00:38:52 -0800 (PST)
- Cc: cgen at sourceware dot cygnus dot com
- References: <200101180826.BAA02239@kayak.mcgary.org>
Greg McGary writes:
> What's the recommended way of handling simulator semantics for a
> general register zero that always reads as 0, and writes as bit-bucket
> (as for MIPS)? Without CGEN support, I'll need to wrap a test for
> reg# 0 as destination around the semantics of every insn that modifies
> registers.
This is handled in the sparc port by having get/set wrappers,
and putting the test there. see sparc.cpu.