Re: How to handle MIPS-like general register 0?

[Ben Elliston <bje at redhat dot com>]

   What's the recommended way of handling simulator semantics for a
   general register zero that always reads as 0, and writes as bit-bucket
   (as for MIPS)?  Without CGEN support, I'll need to wrap a test for
   reg# 0 as destination around the semantics of every insn that modifies
   registers.

The clearest way (to the reader of the cpu description) is to define get/set
handlers for the register hardware:

	(get (index)
	   (if (eq index 0)
		(const SI 0)
		(raw-reg h-gr index)))

In the case of MIPS, I suppose the action for setting r0 is to (nop).

Cheers, Ben