incorrect disassembly on vliw / little endian

[Patrick Macdonald <patrickm at redhat dot com>]

Hi,

I'm using cgen on a vliw set with the following characteristics:
16 bit base instruction, 16/32 bit additional bits based on 
the contents of the base instruction, little endian.

I guess it's best to describe my problem with an example:

Let's say I have a 16 bit instruction (0xdead) and a 16 bit 
variable (0xbeef). The assembler writes this to disk as
adde efbe, which is correct.

On disassembly in @port@-dis.c, the first 16 bits are read in to
determine the instruction (0xdead).  It matches with a 32 bit
instruction and the instruction is re-read as a 32 bit, little 
endian instruction causing the full instruction to become 0xbeefdead 
instead of the correct 0xdeadbeef.  

Before I start mangling the code, has anyone else encountered this
or am I just extremely lucky these days?  Thoughts/hints/directions
gladly accepted.

I'm leaning towards adding a check of endianess on the re-read and
flipping the bits if little endian.  Based on the conditions to 
enter the re-read, this would solve the problem for this particular
port without crippling others.  

Patrick