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Getting started...


Hi,

I am working in the field of DSP Engineering and is currently working on
a specification for a new Ultra Low power DSP Core. I am therefore
interested in building a port of the core (as I think it should look
like) that can serve as specification and/or test purposes of the
hardware implementation in VHDL. However, I have the following
fundamental problems:

1) I have successfully installed Guile 1.4
2) When I try to run the ./configure file from the unpacked
cgen-1.0.tar.gz file I get the following messages:

[jnielsen@jnielsen cgen-1.0]$ ./configure
Configuring for a i686-pc-linux-gnu host.
Created "Makefile" in /home/jnielsen/cgen-1.0 using "mt-frag"
Configuring etc...
loading cache ../config.cache
checking for a BSD compatible install... (cached) /usr/bin/install -c
creating ./config.status
creating Makefile

3) When I subsequently try to run Make the following message appears:
[jnielsen@jnielsen cgen-1.0]$ make
make[1]: Entering directory `/home/jnielsen/cgen-1.0/etc'
make[1]: Nothing to be done for `all'.
make[1]: Leaving directory `/home/jnielsen/cgen-1.0/etc'
[jnielsen@jnielsen cgen-1.0]$

4) Conclusion: Not much happened!
5) However, I then try to manually invoke guile and do an opcodes-port
of the m32r using the procedure in section 5.5 of the manual. I can see
that the files are processed but no text outputs are generated. I assume
it is because the install is not done correctly.
I have also tried using the ./configure options specified in the manual
- same result.

6) I use Caldera Open Linux v2.3 using kernel 2.2.14.

I hope someone can help me getting started. I plan to do a complete port
of an existing design before starting on my own, so I can fully
understand the tools.

Thanks in advance.

Jakob.


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