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Re: branch-delay slot semantics questions
- To: lehotsky at earthlink dot net
- Subject: Re: branch-delay slot semantics questions
- From: Ben Elliston <bje at redhat dot com>
- Date: Mon, 14 May 2001 08:41:11 +1000 (EST)
- Cc: cgen at sourceware dot cygnus dot com
- References: <200105111205.IAA04658@iron.>
>>>>> "lehotsky" == lehotsky <lehotsky@earthlink.net> writes:
lehotsky> Is there also any support for dealing with the semantics that
lehotsky> "a branch in the delay-slot is always annulled". I think I can
lehotsky> implement this by having two bits in the ISA's (setup-semantics (..))
lehotsky> code.
On some architectures, certain classes of instructions are forbidden
in the delay slot. If this is what you really want, it's easiest to
detect this condition during instruction extraction ("fetching").
Again, see the fr30/mloop.in for an illustration.
Ben