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Re: 64-bit port using CGEN


Eric Christopher wrote:
> 
> > Is this port internal/private or can I maybe look at your CPU
> > description file?
> >
> 
> Unfortunately it is internal right now.  I could take a look at yours if
> you want to send it by.  What problems are you running into?

CGEN_INSN_INT is typedef:ed as an "unsigned int" and CGEN generates alot
of code that thinks that an insn or operand can fit into a long or int.

(I attach my file)

regards,
johan
; pxs CPU description  -*- Scheme -*-
; Copyright 2001 Johan Rydberg, jrydberg@opencores.org
;
; This program is free software; you can redistribute it and/or modify
; it under the terms of the GNU General Public License as published by
; the Free Software Foundation; either version 2 of the License, or
; (at your option) any later version.
;
; This program is distributed in the hope that it will be useful,
; but WITHOUT ANY WARRANTY; without even the implied warranty of
; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
; GNU General Public License for more details.
;
; You should have received a copy of the GNU General Public License
; along with this program; if not, write to the Free Software
; Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
;

(include "simplify.inc")

(define-arch
  (name pxs)
  (comment "pxs")
  (insn-lsb0? #t)
  (machs pxs)
  (isas pxs)
)


; Attributes


; Instruction set parameters.
 
(define-isa
  ; Name of the ISA.
  (name pxs)

  ; Base insturction length.  The insns is always 64 bits wide.
  (base-insn-bitsize 64)
)


; CPU family definitions.
  
(define-cpu
  ; CPU names must be distinct from the architecture name and machine names.
  ; The "b" suffix stands for "base" and is the convention.
  ; The "f" suffix stands for "family" and is the convention.
  (name pxsbf)
  (comment "pxs base family")
  (endian big)
  (word-bitsize 64)
)

; Generic machine
(define-mach
  (name pxs)
  (comment "generic pxs cpu")
  (cpu pxsbf)
  (bfd-name "pxs")
)


; Model descriptions

(define-model
  (name pxs-1) (comment "pxs generic model")  (attrs)
  (mach pxs)

  ; Nothing special about this.
  (unit u-exec "Execution Unit" () 1 1 () () () ())
)


; Instruction fields.

; Attributes:
;  . PCREL-ADDR  pc relative value (for reloc and disassembly purposes)
;  . ABS-ADDR    absolute address (for reloc and disassembly purposes?)
;  . RESERVED    bits are not used to decode insn, must be all 0

(dnf f-opc       "opcode class"        () 63 3)
(dnf f-ops       "opcode subclass"     () 60 5)

; Flags
(dnf f-flag-1    "flag 1"              () 55 1)
(dnf f-flag-2    "flag 2"              () 54 1)

(dnf f-res-1     "RESERVED 1"          () 53 4)

(dnf f-ra        "register a"          () 43 6)
(dnf f-rb        "register b"          () 49 6)
(dnf f-rd        "register d"          () 37 6)
; Immediates.
(df  f-simm      "signed imm"          () 31 32 INT #f #f)
(dnf f-uimm      "unsigned imm"        () 31 32)

; PC relative, 61-bit (3 shifted to right)
(df f-disp61     "disp61"              (PCREL-ADDR) 60 61 INT
    ((value pc) (sra WI (sub WI value pc) (const 3)))
    ((value pc) (add WI (sll WI value (const 3)) pc)))

; absolute, 61-bit (3 shifted to right)
(df f-abs61      "abs61"               (ABS-ADDR) 60 61 INT
    ((value pc) (sra WI pc     (const 3)))
    ((value pc) (sll WI value  (const 3))))


; Enums.

; insn-class: bits 31-30
(define-normal-insn-enum insn-class "FIXME" () OPC_ f-opc
  (J JL B BL ALU LSU RSU MISC)
)

(define-normal-insn-enum insn-alu   "FIXME" () ALU_ f-ops
  (ADD SUB MUL DIV AND OR XOR NOR SLL SRL SRA NOP11 NOP12 NOP13 NOP14 NOP15
   ADDI SUBI MULI DIVI ANDI ORI XORI NORI SLLI SRLI SRAI)
)

(define-normal-insn-enum insn-lsu   "FIXME" () LSU_ f-ops
  (LQ LW LH LB LQX LWX LHX LBX SQ SW SH SB SQX SWX SHX SBX)
)


; Hardware pieces.
; These entries list the elements of the raw hardware.
; They're also used to provide tables and other elements of the assembly
; language.

(dnh h-pc "program counter" (PC PROFILE) (pc) () () ())

(define-hardware
  (name h-gr) (comment "general registers") (attrs PROFILE)
  (type register DI (64))
  (indices keyword "" 
           (("0"  0)  ("1" 1)   ("2" 2)   ("3" 3)   ("4" 4)   ("5" 5)   ("6" 6)   ("7" 7)
            ("8"  8)  ("9" 9)   ("10" 10) ("11" 11) ("12" 12) ("13" 13) ("14" 14) ("15" 15) 
            ("16" 16) ("17" 17) ("18" 18) ("19" 19) ("20" 20) ("21" 21) ("22" 22) ("23" 23)
            ("24" 24) ("25" 25) ("26" 26) ("27" 27) ("28" 28) ("29" 29) ("30" 30) ("31" 31) 
            ("32" 32) ("33" 33) ("34" 34) ("35" 35) ("36" 36) ("37" 37) ("38" 38) ("39" 39)
            ("40" 40) ("41" 41) ("42" 42) ("43" 43) ("44" 44) ("45" 45) ("46" 46) ("47" 47) 
            ("48" 48) ("49" 49) ("50" 50) ("51" 51) ("52" 52) ("53" 53) ("54" 54) ("55" 55)
            ("56" 56) ("57" 57) ("58" 58) ("59" 59) ("60" 60) ("61" 61) ("62" 62) ("63" 63))) 
)

; Signed or unsigned bit
(define-hardware
  (name h-signed) (comment "signed") (attrs PROFILE)
  (type immediate (UINT 1))
  (values keyword "" (("" 0) ("s" 1)))
)

(define-hardware
  (name h-update) (comment "signed") (attrs PROFILE)
  (type immediate (UINT 1))
  (values keyword "" (("" 0) ("u" 1)))
)

(define-hardware
  (name h-cond) (comment "signed") (attrs PROFILE)
  (type immediate (UINT 1))
  (values keyword "" (("" 0) ("." 1)))
)



; Instruction operands.

(dnop rd      "destination register"       ()          h-gr    f-rd)
(dnop ra      "source register a"          ()          h-gr    f-ra)
(dnop rb      "source register b"          ()          h-gr    f-rb)
(dnop disp-61 "pc-rel 61 bit"              ()          h-iaddr f-disp61)
(dnop abs-61  "abs 61 bit"                 ()          h-iaddr f-abs61)
(dnop uimm    "uimm"                       ()          h-uint  f-uimm)
(dnop simm    "simm"                       ()          h-sint  f-simm)

; Flags
(dnop sf      "signed bit"                 ()          h-signed f-flag-1)
(dnop uf      "update flag"                ()          h-update f-flag-2)
(dnop cf      "update cond flags flag"     ()          h-cond   f-flag-2)


; Instructions.

; Branch releated instructions 

(define-pmacro (branch-insn mnemonic op disp seq)
  (begin
     (dni (.sym mnemonic)
          (.str mnemonic)
          ()
          (.str mnemonic " ${" disp "}")
          (+ op disp)
          seq
          ()
     )
   )
)

(branch-insn j  OPC_J  abs-61  (set pc abs-61))
(branch-insn jl OPC_JL abs-61  (sequence () (set (reg h-gr 3) pc) (set pc abs-61)))
(branch-insn b  OPC_B  disp-61 (set pc disp-61))
(branch-insn bl OPC_BL disp-61 (sequence () (set (reg h-gr 3) pc) (set pc disp-61)))


; ALU related instructions

(define-pmacro (alu-insn-signed mnemonic op opi)
  (begin
     (dni (.sym mnemonic)
          (.str mnemonic)
          ()
          (.str mnemonic "$sf$cf $rb,$ra,$rd")
          (+ OPC_ALU op rb ra rd sf cf (f-uimm 0) (f-res-1 0))
          (set rd (mnemonic ra rb))
          ())
     (dni (.sym mnemonic i)
          (.str mnemonic "i")
          ()
          (.str mnemonic "i$sf$cf $uimm,$ra,$rd")
          (+ OPC_ALU opi rb ra rd sf cf uimm (f-res-1 0))
          (set rd (mnemonic ra uimm))
          ())
   )
)

(define-pmacro (alu-insn-logic mnemonic op opi)
  (begin
     (dni (.sym mnemonic)
          (.str mnemonic)
          ()
          (.str mnemonic "$cf $rb,$ra,$rd")
          (+ OPC_ALU op rb ra rd sf cf (f-uimm 0) (f-res-1 0))
          (set rd (mnemonic ra rb))
          ())
     (dni (.sym mnemonic i)
          (.str mnemonic "i")
          ()
          (.str mnemonic "i$cf $uimm,$ra,$rd")
          (+ OPC_ALU opi rb ra rd sf cf uimm (f-res-1 0))
          (set rd (mnemonic ra uimm))
          ())
   )
)

(alu-insn-signed add ALU_ADD ALU_ADDI)
(alu-insn-signed sub ALU_SUB ALU_SUBI)
(alu-insn-signed mul ALU_MUL ALU_MULI)
(alu-insn-signed div ALU_DIV ALU_DIVI)

(alu-insn-logic  and ALU_AND ALU_ANDI)
(alu-insn-logic  or  ALU_OR  ALU_ORI)
(alu-insn-logic  xor ALU_XOR ALU_XORI)

(alu-insn-logic  sll ALU_SLL ALU_SLLI)
(alu-insn-logic  srl ALU_SRL ALU_SRLI)
(alu-insn-logic  sra ALU_SRA ALU_SRAI)


; LSU related instructions

(define-pmacro (lsu-load-insn mnemonic OP-NORM OP-INDEX MODE)
  (begin
     (dni (.sym mnemonic)
          (.str mnemonic)
          ()
          (.str mnemonic "$sf$uf $simm($ra),$rd")
          (+ OPC_LSU OP-NORM rb ra rd sf cf simm (f-res-1 0))
          (sequence ()
                    (set rd (if DI sf (ext  DI (mem MODE (add ra simm)))
                                      (zext DI (mem MODE (add ra simm)))))
                    (if VOID uf (set ra (add ra simm))))
          ())
     (dni (.sym mnemonic x)
          (.str mnemonic "x")
          ()
          (.str mnemonic "x$sf$uf $rb,$ra,$rd")
          (+ OPC_LSU OP-INDEX rb ra rd sf cf (f-uimm 0) (f-res-1 0))
          (sequence ()
                    (set rd (if DI sf (ext  DI (mem MODE (add rb ra)))
                                      (zext DI (mem MODE (add rb ra)))))
                    (if VOID uf (set ra (add rb ra))))
          ())
   )
)

(define-pmacro (lsu-store-insn mnemonic OP-NORM OP-INDEX MODE)
  (begin
     (dni (.sym mnemonic)
          (.str mnemonic)
          ()
          (.str mnemonic "$uf $rb,$simm($ra)")
          (+ OPC_LSU OP-NORM rb ra rd sf cf simm (f-res-1 0))
          (sequence ()
                    (set (mem MODE (add ra simm)) rb)
                    (if VOID uf (set ra (add ra simm))))
          ())
     (dni (.sym mnemonic x)
          (.str mnemonic "x")
          ()
          (.str mnemonic "x$uf $rb,$rd,$ra")
          (+ OPC_LSU OP-INDEX rb ra rd sf cf (f-uimm 0) (f-res-1 0))
          (sequence ()
                    (set (mem MODE (add ra rd)) rb)
                    (if VOID uf (set ra (add ra rd))))
          ())
   )
)

(lsu-load-insn lq LSU_LQ LSU_LQX DI)
(lsu-load-insn lw LSU_LW LSU_LWX WI)
(lsu-load-insn lh LSU_LH LSU_LHX HI)
(lsu-load-insn lb LSU_LB LSU_LBX QI)

(lsu-store-insn sq LSU_SQ LSU_SQX DI)
(lsu-store-insn sw LSU_SW LSU_SWX DI)
(lsu-store-insn sh LSU_SH LSU_SHX DI)
(lsu-store-insn sb LSU_SB LSU_SBX DI)





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