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[patch] Instruction and Cycle Counting
- From: Dave Brolley <brolley at redhat dot com>
- To: cgen at sources dot redhat dot com
- Date: Wed, 15 Jan 2003 15:06:36 -0500
- Subject: [patch] Instruction and Cycle Counting
This patch corrects the instruction count and cycle count printed by
--final-insn-count.
Approved by Ben Elliston and committed.
Dave
2003-01-15 Dave Brolley <brolley@redhat.com>
* compCGEN.cxx (cgen_bi_endian_cpu): Don't initialize trace_count.
(trace_counter): Use total_insn_count and total_latency.
* cgen-cpu.h (class cgen_bi_endian_cpu): Remove trace_count.
2003-01-15 Dave Brolley <brolley@redhat.com>
* sidcpuutil.h (sidutil): Add total_insn_count when computing
simulated cycles.
Index: sid/component/cgen-cpu/cgen-cpu.h
===================================================================
RCS file: /cvs/src/src/sid/component/cgen-cpu/cgen-cpu.h,v
retrieving revision 1.8
diff -c -p -r1.8 cgen-cpu.h
*** sid/component/cgen-cpu/cgen-cpu.h 7 Feb 2002 17:32:28 -0000 1.8
--- sid/component/cgen-cpu/cgen-cpu.h 15 Jan 2003 19:55:16 -0000
***************
*** 1,6 ****
// cgen-cpu.h -*- C++ -*-
! // Copyright (C) 2000, 2001, 2002 Red Hat.
// This file is part of SID and is licensed under the GPL.
// See the file COPYING.SID for conditions for redistribution.
--- 1,6 ----
// cgen-cpu.h -*- C++ -*-
! // Copyright (C) 2000, 2001, 2002, 2003 Red Hat.
// This file is part of SID and is licensed under the GPL.
// See the file COPYING.SID for conditions for redistribution.
*************** protected:
*** 80,86 ****
static int cgen_symbol_at_address(bfd_vma addr, struct disassemble_info * info);
// Counter tracing support
void trace_counter (PCADDR pc);
- host_int_8 trace_count;
public:
cgen_bi_endian_cpu ();
--- 80,85 ----
Index: sid/component/cgen-cpu/compCGEN.cxx
===================================================================
RCS file: /cvs/src/src/sid/component/cgen-cpu/compCGEN.cxx,v
retrieving revision 1.10
diff -c -p -r1.10 compCGEN.cxx
*** sid/component/cgen-cpu/compCGEN.cxx 8 Jan 2003 04:08:29 -0000 1.10
--- sid/component/cgen-cpu/compCGEN.cxx 15 Jan 2003 19:55:16 -0000
***************
*** 1,6 ****
// compCGEN.cxx - CPU components. -*- C++ -*-
! // Copyright (C) 1999, 2000, 2001, 2002 Red Hat.
// This file is part of SID and is licensed under the GPL.
// See the file COPYING.SID for conditions for redistribution.
--- 1,6 ----
// compCGEN.cxx - CPU components. -*- C++ -*-
! // Copyright (C) 1999, 2000, 2001, 2002, 2003 Red Hat.
// This file is part of SID and is licensed under the GPL.
// See the file COPYING.SID for conditions for redistribution.
*************** using namespace cgen;
*** 39,45 ****
// ----------------------------------------------------------------------------
cgen_bi_endian_cpu::cgen_bi_endian_cpu ()
{
- trace_count = 0;
warnings_enabled = false;
add_attribute ("enable-warnings?", & warnings_enabled, "setting");
this->engine_type = ENGINE_UNKNOWN;
--- 39,44 ----
*************** void
*** 260,270 ****
cgen_bi_endian_cpu::trace_counter (PCADDR pc)
{
this->trace_stream
! << this->trace_count++ << ' '
! << (this->sched_query.now()-1) << '\t';
!
! // Invalidate any local icaches; they distort approximate cycle counting.
! this->flush_icache (pc);
}
--- 259,266 ----
cgen_bi_endian_cpu::trace_counter (PCADDR pc)
{
this->trace_stream
! << this->total_insn_count << ' '
! << this->total_insn_count + this->total_latency << '\t';
}
Index: sid/component/cgen-cpu/m32r/m32r-cpu.h
===================================================================
RCS file: /cvs/src/src/sid/component/cgen-cpu/m32r/m32r-cpu.h,v
retrieving revision 1.1
diff -c -p -r1.1 m32r-cpu.h
*** sid/component/cgen-cpu/m32r/m32r-cpu.h 7 Dec 2000 19:30:49 -0000 1.1
--- sid/component/cgen-cpu/m32r/m32r-cpu.h 15 Jan 2003 19:55:16 -0000
***************
*** 2,10 ****
THIS FILE IS MACHINE GENERATED WITH CGEN.
! Copyright (C) 2000 Red Hat, Inc.
! This file is part of the Cygnus Simulators.
*/
--- 2,10 ----
THIS FILE IS MACHINE GENERATED WITH CGEN.
! Copyright (C) 2000, 2001 Red Hat, Inc.
! This file is part of the Red Hat simulators.
*/
Index: sid/component/cgen-cpu/m32r/m32r-decode.cxx
===================================================================
RCS file: /cvs/src/src/sid/component/cgen-cpu/m32r/m32r-decode.cxx,v
retrieving revision 1.2
diff -c -p -r1.2 m32r-decode.cxx
*** sid/component/cgen-cpu/m32r/m32r-decode.cxx 1 Mar 2001 19:15:33 -0000 1.2
--- sid/component/cgen-cpu/m32r/m32r-decode.cxx 15 Jan 2003 19:55:16 -0000
***************
*** 2,10 ****
THIS FILE IS MACHINE GENERATED WITH CGEN.
! Copyright (C) 2000 Red Hat, Inc.
! This file is part of the Cygnus Simulators.
*/
--- 2,10 ----
THIS FILE IS MACHINE GENERATED WITH CGEN.
! Copyright (C) 2000, 2001 Red Hat, Inc.
! This file is part of the Red Hat simulators.
*/
*************** using namespace m32rbf; // FIXME: namesp
*** 17,23 ****
// The instruction descriptor array.
! m32rbf_idesc m32rbf_idesc::idesc_table[M32RBF_INSN_MAX] =
{
{ m32rbf_sem_x_invalid, "X_INVALID", M32RBF_INSN_X_INVALID, { 0|(1<<CGEN_INSN_VIRTUAL), (1<<MACH_BASE), PIPE_NONE } },
{ m32rbf_sem_add, "ADD", M32RBF_INSN_ADD, { 0, (1<<MACH_BASE), PIPE_OS } },
--- 17,23 ----
// The instruction descriptor array.
! m32rbf_idesc m32rbf_idesc::idesc_table[M32RBF_INSN_UNLOCK + 1] =
{
{ m32rbf_sem_x_invalid, "X_INVALID", M32RBF_INSN_X_INVALID, { 0|(1<<CGEN_INSN_VIRTUAL), (1<<MACH_BASE), PIPE_NONE } },
{ m32rbf_sem_add, "ADD", M32RBF_INSN_ADD, { 0, (1<<MACH_BASE), PIPE_OS } },
*************** m32rbf_extract_sfmt_ld (m32rbf_scache* a
*** 187,192 ****
--- 187,200 ----
static void
m32rbf_extract_sfmt_ld_d (m32rbf_scache* abuf, m32rbf_cpu* current_cpu, PCADDR pc, m32rbf_insn_word base_insn, m32rbf_insn_word entire_insn);
static void
+ m32rbf_extract_sfmt_ldb (m32rbf_scache* abuf, m32rbf_cpu* current_cpu, PCADDR pc, m32rbf_insn_word base_insn, m32rbf_insn_word entire_insn);
+ static void
+ m32rbf_extract_sfmt_ldb_d (m32rbf_scache* abuf, m32rbf_cpu* current_cpu, PCADDR pc, m32rbf_insn_word base_insn, m32rbf_insn_word entire_insn);
+ static void
+ m32rbf_extract_sfmt_ldh (m32rbf_scache* abuf, m32rbf_cpu* current_cpu, PCADDR pc, m32rbf_insn_word base_insn, m32rbf_insn_word entire_insn);
+ static void
+ m32rbf_extract_sfmt_ldh_d (m32rbf_scache* abuf, m32rbf_cpu* current_cpu, PCADDR pc, m32rbf_insn_word base_insn, m32rbf_insn_word entire_insn);
+ static void
m32rbf_extract_sfmt_ld_plus (m32rbf_scache* abuf, m32rbf_cpu* current_cpu, PCADDR pc, m32rbf_insn_word base_insn, m32rbf_insn_word entire_insn);
static void
m32rbf_extract_sfmt_ld24 (m32rbf_scache* abuf, m32rbf_cpu* current_cpu, PCADDR pc, m32rbf_insn_word base_insn, m32rbf_insn_word entire_insn);
*************** m32rbf_scache::decode (m32rbf_cpu* curre
*** 252,313 ****
m32rbf_insn_word insn = base_insn;
{
! unsigned int val = (((insn >> 8) & (15 << 4)) | ((insn >> 4) & (15 << 0)));
switch (val)
{
! case 0 : itype = M32RBF_INSN_SUBV; m32rbf_extract_sfmt_addv (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 1 : itype = M32RBF_INSN_SUBX; m32rbf_extract_sfmt_addx (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 2 : itype = M32RBF_INSN_SUB; m32rbf_extract_sfmt_add (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 3 : itype = M32RBF_INSN_NEG; m32rbf_extract_sfmt_mv (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 4 : itype = M32RBF_INSN_CMP; m32rbf_extract_sfmt_cmp (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 5 : itype = M32RBF_INSN_CMPU; m32rbf_extract_sfmt_cmp (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 8 : itype = M32RBF_INSN_ADDV; m32rbf_extract_sfmt_addv (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 9 : itype = M32RBF_INSN_ADDX; m32rbf_extract_sfmt_addx (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 10 : itype = M32RBF_INSN_ADD; m32rbf_extract_sfmt_add (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 11 : itype = M32RBF_INSN_NOT; m32rbf_extract_sfmt_mv (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 12 : itype = M32RBF_INSN_AND; m32rbf_extract_sfmt_add (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 13 : itype = M32RBF_INSN_XOR; m32rbf_extract_sfmt_add (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 14 : itype = M32RBF_INSN_OR; m32rbf_extract_sfmt_add (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 16 : itype = M32RBF_INSN_SRL; m32rbf_extract_sfmt_add (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 18 : itype = M32RBF_INSN_SRA; m32rbf_extract_sfmt_add (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 20 : itype = M32RBF_INSN_SLL; m32rbf_extract_sfmt_add (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 22 : itype = M32RBF_INSN_MUL; m32rbf_extract_sfmt_add (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 24 : itype = M32RBF_INSN_MV; m32rbf_extract_sfmt_mv (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 25 : itype = M32RBF_INSN_MVFC; m32rbf_extract_sfmt_mvfc (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 26 : itype = M32RBF_INSN_MVTC; m32rbf_extract_sfmt_mvtc (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 28 :
{
! unsigned int val = (((insn >> 8) & (1 << 0)));
switch (val)
{
! case 0 : itype = M32RBF_INSN_JL; m32rbf_extract_sfmt_jl (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 1 : itype = M32RBF_INSN_JMP; m32rbf_extract_sfmt_jmp (this, current_cpu, pc, base_insn, entire_insn); goto done;
default : itype = M32RBF_INSN_X_INVALID; m32rbf_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
}
}
! case 29 : itype = M32RBF_INSN_RTE; m32rbf_extract_sfmt_rte (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 31 : itype = M32RBF_INSN_TRAP; m32rbf_extract_sfmt_trap (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 32 : itype = M32RBF_INSN_STB; m32rbf_extract_sfmt_stb (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 34 : itype = M32RBF_INSN_STH; m32rbf_extract_sfmt_sth (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 36 : itype = M32RBF_INSN_ST; m32rbf_extract_sfmt_st (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 37 : itype = M32RBF_INSN_UNLOCK; m32rbf_extract_sfmt_unlock (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 38 : itype = M32RBF_INSN_ST_PLUS; m32rbf_extract_sfmt_st_plus (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 39 : itype = M32RBF_INSN_ST_MINUS; m32rbf_extract_sfmt_st_plus (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 40 : itype = M32RBF_INSN_LDB; m32rbf_extract_sfmt_ld (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 41 : itype = M32RBF_INSN_LDUB; m32rbf_extract_sfmt_ld (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 42 : itype = M32RBF_INSN_LDH; m32rbf_extract_sfmt_ld (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 43 : itype = M32RBF_INSN_LDUH; m32rbf_extract_sfmt_ld (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 44 : itype = M32RBF_INSN_LD; m32rbf_extract_sfmt_ld (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 45 : itype = M32RBF_INSN_LOCK; m32rbf_extract_sfmt_lock (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 46 : itype = M32RBF_INSN_LD_PLUS; m32rbf_extract_sfmt_ld_plus (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 48 : itype = M32RBF_INSN_MULHI; m32rbf_extract_sfmt_mulhi (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 49 : itype = M32RBF_INSN_MULLO; m32rbf_extract_sfmt_mulhi (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 50 : itype = M32RBF_INSN_MULWHI; m32rbf_extract_sfmt_mulhi (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 51 : itype = M32RBF_INSN_MULWLO; m32rbf_extract_sfmt_mulhi (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 52 : itype = M32RBF_INSN_MACHI; m32rbf_extract_sfmt_machi (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 53 : itype = M32RBF_INSN_MACLO; m32rbf_extract_sfmt_machi (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 54 : itype = M32RBF_INSN_MACWHI; m32rbf_extract_sfmt_machi (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 55 : itype = M32RBF_INSN_MACWLO; m32rbf_extract_sfmt_machi (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 64 : /* fall through */
case 65 : /* fall through */
case 66 : /* fall through */
--- 260,321 ----
m32rbf_insn_word insn = base_insn;
{
! unsigned int val = (((insn >> 24) & (15 << 4)) | ((insn >> 20) & (15 << 0)));
switch (val)
{
! case 0 : itype = M32RBF_INSN_SUBV; m32rbf_extract_sfmt_addv (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 1 : itype = M32RBF_INSN_SUBX; m32rbf_extract_sfmt_addx (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 2 : itype = M32RBF_INSN_SUB; m32rbf_extract_sfmt_add (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 3 : itype = M32RBF_INSN_NEG; m32rbf_extract_sfmt_mv (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 4 : itype = M32RBF_INSN_CMP; m32rbf_extract_sfmt_cmp (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 5 : itype = M32RBF_INSN_CMPU; m32rbf_extract_sfmt_cmp (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 8 : itype = M32RBF_INSN_ADDV; m32rbf_extract_sfmt_addv (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 9 : itype = M32RBF_INSN_ADDX; m32rbf_extract_sfmt_addx (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 10 : itype = M32RBF_INSN_ADD; m32rbf_extract_sfmt_add (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 11 : itype = M32RBF_INSN_NOT; m32rbf_extract_sfmt_mv (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 12 : itype = M32RBF_INSN_AND; m32rbf_extract_sfmt_add (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 13 : itype = M32RBF_INSN_XOR; m32rbf_extract_sfmt_add (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 14 : itype = M32RBF_INSN_OR; m32rbf_extract_sfmt_add (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 16 : itype = M32RBF_INSN_SRL; m32rbf_extract_sfmt_add (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 18 : itype = M32RBF_INSN_SRA; m32rbf_extract_sfmt_add (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 20 : itype = M32RBF_INSN_SLL; m32rbf_extract_sfmt_add (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 22 : itype = M32RBF_INSN_MUL; m32rbf_extract_sfmt_add (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 24 : itype = M32RBF_INSN_MV; m32rbf_extract_sfmt_mv (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 25 : itype = M32RBF_INSN_MVFC; m32rbf_extract_sfmt_mvfc (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 26 : itype = M32RBF_INSN_MVTC; m32rbf_extract_sfmt_mvtc (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 28 :
{
! unsigned int val = (((insn >> 24) & (1 << 0)));
switch (val)
{
! case 0 : itype = M32RBF_INSN_JL; m32rbf_extract_sfmt_jl (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 1 : itype = M32RBF_INSN_JMP; m32rbf_extract_sfmt_jmp (this, current_cpu, pc, base_insn, entire_insn); goto done;
default : itype = M32RBF_INSN_X_INVALID; m32rbf_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
}
}
! case 29 : itype = M32RBF_INSN_RTE; m32rbf_extract_sfmt_rte (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 31 : itype = M32RBF_INSN_TRAP; m32rbf_extract_sfmt_trap (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 32 : itype = M32RBF_INSN_STB; m32rbf_extract_sfmt_stb (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 34 : itype = M32RBF_INSN_STH; m32rbf_extract_sfmt_sth (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 36 : itype = M32RBF_INSN_ST; m32rbf_extract_sfmt_st (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 37 : itype = M32RBF_INSN_UNLOCK; m32rbf_extract_sfmt_unlock (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 38 : itype = M32RBF_INSN_ST_PLUS; m32rbf_extract_sfmt_st_plus (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 39 : itype = M32RBF_INSN_ST_MINUS; m32rbf_extract_sfmt_st_plus (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 40 : itype = M32RBF_INSN_LDB; m32rbf_extract_sfmt_ldb (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 41 : itype = M32RBF_INSN_LDUB; m32rbf_extract_sfmt_ldb (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 42 : itype = M32RBF_INSN_LDH; m32rbf_extract_sfmt_ldh (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 43 : itype = M32RBF_INSN_LDUH; m32rbf_extract_sfmt_ldh (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 44 : itype = M32RBF_INSN_LD; m32rbf_extract_sfmt_ld (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 45 : itype = M32RBF_INSN_LOCK; m32rbf_extract_sfmt_lock (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 46 : itype = M32RBF_INSN_LD_PLUS; m32rbf_extract_sfmt_ld_plus (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 48 : itype = M32RBF_INSN_MULHI; m32rbf_extract_sfmt_mulhi (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 49 : itype = M32RBF_INSN_MULLO; m32rbf_extract_sfmt_mulhi (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 50 : itype = M32RBF_INSN_MULWHI; m32rbf_extract_sfmt_mulhi (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 51 : itype = M32RBF_INSN_MULWLO; m32rbf_extract_sfmt_mulhi (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 52 : itype = M32RBF_INSN_MACHI; m32rbf_extract_sfmt_machi (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 53 : itype = M32RBF_INSN_MACLO; m32rbf_extract_sfmt_machi (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 54 : itype = M32RBF_INSN_MACWHI; m32rbf_extract_sfmt_machi (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 55 : itype = M32RBF_INSN_MACWLO; m32rbf_extract_sfmt_machi (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 64 : /* fall through */
case 65 : /* fall through */
case 66 : /* fall through */
*************** m32rbf_scache::decode (m32rbf_cpu* curre
*** 323,355 ****
case 76 : /* fall through */
case 77 : /* fall through */
case 78 : /* fall through */
! case 79 : itype = M32RBF_INSN_ADDI; m32rbf_extract_sfmt_addi (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 80 : /* fall through */
! case 81 : itype = M32RBF_INSN_SRLI; m32rbf_extract_sfmt_slli (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 82 : /* fall through */
! case 83 : itype = M32RBF_INSN_SRAI; m32rbf_extract_sfmt_slli (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 84 : /* fall through */
! case 85 : itype = M32RBF_INSN_SLLI; m32rbf_extract_sfmt_slli (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 87 :
{
! unsigned int val = (((insn >> 0) & (1 << 0)));
switch (val)
{
! case 0 : itype = M32RBF_INSN_MVTACHI; m32rbf_extract_sfmt_mvtachi (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 1 : itype = M32RBF_INSN_MVTACLO; m32rbf_extract_sfmt_mvtachi (this, current_cpu, pc, base_insn, entire_insn); goto done;
default : itype = M32RBF_INSN_X_INVALID; m32rbf_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
}
}
! case 88 : itype = M32RBF_INSN_RACH; m32rbf_extract_sfmt_rac (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 89 : itype = M32RBF_INSN_RAC; m32rbf_extract_sfmt_rac (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 95 :
{
! unsigned int val = (((insn >> 0) & (3 << 0)));
switch (val)
{
! case 0 : itype = M32RBF_INSN_MVFACHI; m32rbf_extract_sfmt_mvfachi (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 1 : itype = M32RBF_INSN_MVFACLO; m32rbf_extract_sfmt_mvfachi (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 2 : itype = M32RBF_INSN_MVFACMI; m32rbf_extract_sfmt_mvfachi (this, current_cpu, pc, base_insn, entire_insn); goto done;
default : itype = M32RBF_INSN_X_INVALID; m32rbf_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
}
}
--- 331,363 ----
case 76 : /* fall through */
case 77 : /* fall through */
case 78 : /* fall through */
! case 79 : itype = M32RBF_INSN_ADDI; m32rbf_extract_sfmt_addi (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 80 : /* fall through */
! case 81 : itype = M32RBF_INSN_SRLI; m32rbf_extract_sfmt_slli (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 82 : /* fall through */
! case 83 : itype = M32RBF_INSN_SRAI; m32rbf_extract_sfmt_slli (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 84 : /* fall through */
! case 85 : itype = M32RBF_INSN_SLLI; m32rbf_extract_sfmt_slli (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 87 :
{
! unsigned int val = (((insn >> 16) & (1 << 0)));
switch (val)
{
! case 0 : itype = M32RBF_INSN_MVTACHI; m32rbf_extract_sfmt_mvtachi (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 1 : itype = M32RBF_INSN_MVTACLO; m32rbf_extract_sfmt_mvtachi (this, current_cpu, pc, base_insn, entire_insn); goto done;
default : itype = M32RBF_INSN_X_INVALID; m32rbf_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
}
}
! case 88 : itype = M32RBF_INSN_RACH; m32rbf_extract_sfmt_rac (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 89 : itype = M32RBF_INSN_RAC; m32rbf_extract_sfmt_rac (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 95 :
{
! unsigned int val = (((insn >> 16) & (3 << 0)));
switch (val)
{
! case 0 : itype = M32RBF_INSN_MVFACHI; m32rbf_extract_sfmt_mvfachi (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 1 : itype = M32RBF_INSN_MVFACLO; m32rbf_extract_sfmt_mvfachi (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 2 : itype = M32RBF_INSN_MVFACMI; m32rbf_extract_sfmt_mvfachi (this, current_cpu, pc, base_insn, entire_insn); goto done;
default : itype = M32RBF_INSN_X_INVALID; m32rbf_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
}
}
*************** m32rbf_scache::decode (m32rbf_cpu* curre
*** 368,384 ****
case 108 : /* fall through */
case 109 : /* fall through */
case 110 : /* fall through */
! case 111 : itype = M32RBF_INSN_LDI8; m32rbf_extract_sfmt_ldi8 (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 112 :
{
! unsigned int val = (((insn >> 8) & (15 << 0)));
switch (val)
{
! case 0 : itype = M32RBF_INSN_NOP; m32rbf_extract_sfmt_nop (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 12 : itype = M32RBF_INSN_BC8; m32rbf_extract_sfmt_bc8 (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 13 : itype = M32RBF_INSN_BNC8; m32rbf_extract_sfmt_bc8 (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 14 : itype = M32RBF_INSN_BL8; m32rbf_extract_sfmt_bl8 (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 15 : itype = M32RBF_INSN_BRA8; m32rbf_extract_sfmt_bra8 (this, current_cpu, pc, base_insn, entire_insn); goto done;
default : itype = M32RBF_INSN_X_INVALID; m32rbf_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
}
}
--- 376,392 ----
case 108 : /* fall through */
case 109 : /* fall through */
case 110 : /* fall through */
! case 111 : itype = M32RBF_INSN_LDI8; m32rbf_extract_sfmt_ldi8 (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 112 :
{
! unsigned int val = (((insn >> 24) & (15 << 0)));
switch (val)
{
! case 0 : itype = M32RBF_INSN_NOP; m32rbf_extract_sfmt_nop (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 12 : itype = M32RBF_INSN_BC8; m32rbf_extract_sfmt_bc8 (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 13 : itype = M32RBF_INSN_BNC8; m32rbf_extract_sfmt_bc8 (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 14 : itype = M32RBF_INSN_BL8; m32rbf_extract_sfmt_bl8 (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 15 : itype = M32RBF_INSN_BRA8; m32rbf_extract_sfmt_bra8 (this, current_cpu, pc, base_insn, entire_insn); goto done;
default : itype = M32RBF_INSN_X_INVALID; m32rbf_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
}
}
*************** m32rbf_scache::decode (m32rbf_cpu* curre
*** 398,445 ****
case 126 : /* fall through */
case 127 :
{
! unsigned int val = (((insn >> 8) & (3 << 0)));
switch (val)
{
! case 0 : itype = M32RBF_INSN_BC8; m32rbf_extract_sfmt_bc8 (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 1 : itype = M32RBF_INSN_BNC8; m32rbf_extract_sfmt_bc8 (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 2 : itype = M32RBF_INSN_BL8; m32rbf_extract_sfmt_bl8 (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 3 : itype = M32RBF_INSN_BRA8; m32rbf_extract_sfmt_bra8 (this, current_cpu, pc, base_insn, entire_insn); goto done;
default : itype = M32RBF_INSN_X_INVALID; m32rbf_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
}
}
! case 132 : itype = M32RBF_INSN_CMPI; m32rbf_extract_sfmt_cmpi (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 133 : itype = M32RBF_INSN_CMPUI; m32rbf_extract_sfmt_cmpi (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 136 : itype = M32RBF_INSN_ADDV3; m32rbf_extract_sfmt_addv3 (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 138 : itype = M32RBF_INSN_ADD3; m32rbf_extract_sfmt_add3 (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 140 : itype = M32RBF_INSN_AND3; m32rbf_extract_sfmt_and3 (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 141 : itype = M32RBF_INSN_XOR3; m32rbf_extract_sfmt_and3 (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 142 : itype = M32RBF_INSN_OR3; m32rbf_extract_sfmt_or3 (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 144 : itype = M32RBF_INSN_DIV; m32rbf_extract_sfmt_div (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 145 : itype = M32RBF_INSN_DIVU; m32rbf_extract_sfmt_div (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 146 : itype = M32RBF_INSN_REM; m32rbf_extract_sfmt_div (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 147 : itype = M32RBF_INSN_REMU; m32rbf_extract_sfmt_div (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 152 : itype = M32RBF_INSN_SRL3; m32rbf_extract_sfmt_sll3 (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 154 : itype = M32RBF_INSN_SRA3; m32rbf_extract_sfmt_sll3 (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 156 : itype = M32RBF_INSN_SLL3; m32rbf_extract_sfmt_sll3 (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 159 : itype = M32RBF_INSN_LDI16; m32rbf_extract_sfmt_ldi16 (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 160 : itype = M32RBF_INSN_STB_D; m32rbf_extract_sfmt_stb_d (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 162 : itype = M32RBF_INSN_STH_D; m32rbf_extract_sfmt_sth_d (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 164 : itype = M32RBF_INSN_ST_D; m32rbf_extract_sfmt_st_d (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 168 : itype = M32RBF_INSN_LDB_D; m32rbf_extract_sfmt_ld_d (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 169 : itype = M32RBF_INSN_LDUB_D; m32rbf_extract_sfmt_ld_d (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 170 : itype = M32RBF_INSN_LDH_D; m32rbf_extract_sfmt_ld_d (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 171 : itype = M32RBF_INSN_LDUH_D; m32rbf_extract_sfmt_ld_d (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 172 : itype = M32RBF_INSN_LD_D; m32rbf_extract_sfmt_ld_d (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 176 : itype = M32RBF_INSN_BEQ; m32rbf_extract_sfmt_beq (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 177 : itype = M32RBF_INSN_BNE; m32rbf_extract_sfmt_beq (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 184 : itype = M32RBF_INSN_BEQZ; m32rbf_extract_sfmt_beqz (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 185 : itype = M32RBF_INSN_BNEZ; m32rbf_extract_sfmt_beqz (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 186 : itype = M32RBF_INSN_BLTZ; m32rbf_extract_sfmt_beqz (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 187 : itype = M32RBF_INSN_BGEZ; m32rbf_extract_sfmt_beqz (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 188 : itype = M32RBF_INSN_BLEZ; m32rbf_extract_sfmt_beqz (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 189 : itype = M32RBF_INSN_BGTZ; m32rbf_extract_sfmt_beqz (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 220 : itype = M32RBF_INSN_SETH; m32rbf_extract_sfmt_seth (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 224 : /* fall through */
case 225 : /* fall through */
case 226 : /* fall through */
--- 406,453 ----
case 126 : /* fall through */
case 127 :
{
! unsigned int val = (((insn >> 24) & (3 << 0)));
switch (val)
{
! case 0 : itype = M32RBF_INSN_BC8; m32rbf_extract_sfmt_bc8 (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 1 : itype = M32RBF_INSN_BNC8; m32rbf_extract_sfmt_bc8 (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 2 : itype = M32RBF_INSN_BL8; m32rbf_extract_sfmt_bl8 (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 3 : itype = M32RBF_INSN_BRA8; m32rbf_extract_sfmt_bra8 (this, current_cpu, pc, base_insn, entire_insn); goto done;
default : itype = M32RBF_INSN_X_INVALID; m32rbf_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
}
}
! case 132 : itype = M32RBF_INSN_CMPI; m32rbf_extract_sfmt_cmpi (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 133 : itype = M32RBF_INSN_CMPUI; m32rbf_extract_sfmt_cmpi (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 136 : itype = M32RBF_INSN_ADDV3; m32rbf_extract_sfmt_addv3 (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 138 : itype = M32RBF_INSN_ADD3; m32rbf_extract_sfmt_add3 (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 140 : itype = M32RBF_INSN_AND3; m32rbf_extract_sfmt_and3 (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 141 : itype = M32RBF_INSN_XOR3; m32rbf_extract_sfmt_and3 (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 142 : itype = M32RBF_INSN_OR3; m32rbf_extract_sfmt_or3 (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 144 : itype = M32RBF_INSN_DIV; m32rbf_extract_sfmt_div (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 145 : itype = M32RBF_INSN_DIVU; m32rbf_extract_sfmt_div (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 146 : itype = M32RBF_INSN_REM; m32rbf_extract_sfmt_div (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 147 : itype = M32RBF_INSN_REMU; m32rbf_extract_sfmt_div (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 152 : itype = M32RBF_INSN_SRL3; m32rbf_extract_sfmt_sll3 (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 154 : itype = M32RBF_INSN_SRA3; m32rbf_extract_sfmt_sll3 (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 156 : itype = M32RBF_INSN_SLL3; m32rbf_extract_sfmt_sll3 (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 159 : itype = M32RBF_INSN_LDI16; m32rbf_extract_sfmt_ldi16 (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 160 : itype = M32RBF_INSN_STB_D; m32rbf_extract_sfmt_stb_d (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 162 : itype = M32RBF_INSN_STH_D; m32rbf_extract_sfmt_sth_d (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 164 : itype = M32RBF_INSN_ST_D; m32rbf_extract_sfmt_st_d (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 168 : itype = M32RBF_INSN_LDB_D; m32rbf_extract_sfmt_ldb_d (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 169 : itype = M32RBF_INSN_LDUB_D; m32rbf_extract_sfmt_ldb_d (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 170 : itype = M32RBF_INSN_LDH_D; m32rbf_extract_sfmt_ldh_d (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 171 : itype = M32RBF_INSN_LDUH_D; m32rbf_extract_sfmt_ldh_d (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 172 : itype = M32RBF_INSN_LD_D; m32rbf_extract_sfmt_ld_d (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 176 : itype = M32RBF_INSN_BEQ; m32rbf_extract_sfmt_beq (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 177 : itype = M32RBF_INSN_BNE; m32rbf_extract_sfmt_beq (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 184 : itype = M32RBF_INSN_BEQZ; m32rbf_extract_sfmt_beqz (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 185 : itype = M32RBF_INSN_BNEZ; m32rbf_extract_sfmt_beqz (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 186 : itype = M32RBF_INSN_BLTZ; m32rbf_extract_sfmt_beqz (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 187 : itype = M32RBF_INSN_BGEZ; m32rbf_extract_sfmt_beqz (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 188 : itype = M32RBF_INSN_BLEZ; m32rbf_extract_sfmt_beqz (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 189 : itype = M32RBF_INSN_BGTZ; m32rbf_extract_sfmt_beqz (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 220 : itype = M32RBF_INSN_SETH; m32rbf_extract_sfmt_seth (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 224 : /* fall through */
case 225 : /* fall through */
case 226 : /* fall through */
*************** m32rbf_scache::decode (m32rbf_cpu* curre
*** 455,461 ****
case 236 : /* fall through */
case 237 : /* fall through */
case 238 : /* fall through */
! case 239 : itype = M32RBF_INSN_LD24; m32rbf_extract_sfmt_ld24 (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 240 : /* fall through */
case 241 : /* fall through */
case 242 : /* fall through */
--- 463,469 ----
case 236 : /* fall through */
case 237 : /* fall through */
case 238 : /* fall through */
! case 239 : itype = M32RBF_INSN_LD24; m32rbf_extract_sfmt_ld24 (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 240 : /* fall through */
case 241 : /* fall through */
case 242 : /* fall through */
*************** m32rbf_scache::decode (m32rbf_cpu* curre
*** 473,485 ****
case 254 : /* fall through */
case 255 :
{
! unsigned int val = (((insn >> 8) & (3 << 0)));
switch (val)
{
! case 0 : itype = M32RBF_INSN_BC24; m32rbf_extract_sfmt_bc24 (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 1 : itype = M32RBF_INSN_BNC24; m32rbf_extract_sfmt_bc24 (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 2 : itype = M32RBF_INSN_BL24; m32rbf_extract_sfmt_bl24 (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 3 : itype = M32RBF_INSN_BRA24; m32rbf_extract_sfmt_bra24 (this, current_cpu, pc, base_insn, entire_insn); goto done;
default : itype = M32RBF_INSN_X_INVALID; m32rbf_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
}
}
--- 481,493 ----
case 254 : /* fall through */
case 255 :
{
! unsigned int val = (((insn >> 24) & (3 << 0)));
switch (val)
{
! case 0 : itype = M32RBF_INSN_BC24; m32rbf_extract_sfmt_bc24 (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 1 : itype = M32RBF_INSN_BNC24; m32rbf_extract_sfmt_bc24 (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 2 : itype = M32RBF_INSN_BL24; m32rbf_extract_sfmt_bl24 (this, current_cpu, pc, base_insn, entire_insn); goto done;
! case 3 : itype = M32RBF_INSN_BRA24; m32rbf_extract_sfmt_bra24 (this, current_cpu, pc, base_insn, entire_insn); goto done;
default : itype = M32RBF_INSN_X_INVALID; m32rbf_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
}
}
*************** m32rbf_extract_sfmt_ld_d (m32rbf_scache*
*** 1095,1100 ****
--- 1103,1224 ----
{
current_cpu->trace_stream
<< "0x" << hex << pc << dec << " (sfmt_ld_d)\t"
+ << " f_simm16:0x" << hex << f_simm16 << dec
+ << " f_r2:0x" << hex << f_r2 << dec
+ << " f_r1:0x" << hex << f_r1 << dec
+ << endl;
+ }
+
+ #undef FLD
+ }
+
+ void
+ m32rbf_extract_sfmt_ldb (m32rbf_scache* abuf, m32rbf_cpu* current_cpu, PCADDR pc, m32rbf_insn_word base_insn, m32rbf_insn_word entire_insn){
+ m32rbf_insn_word insn = entire_insn;
+ #define FLD(f) abuf->fields.sfmt_and3.f
+ UINT f_r1;
+ UINT f_r2;
+
+ f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
+ f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_r2) = f_r2;
+ FLD (f_r1) = f_r1;
+ FLD (i_sr) = & current_cpu->hardware.h_gr[f_r2];
+ FLD (i_dr) = & current_cpu->hardware.h_gr[f_r1];
+ if (UNLIKELY(current_cpu->trace_extract_p))
+ {
+ current_cpu->trace_stream
+ << "0x" << hex << pc << dec << " (sfmt_ldb)\t"
+ << " f_r2:0x" << hex << f_r2 << dec
+ << " f_r1:0x" << hex << f_r1 << dec
+ << endl;
+ }
+
+ #undef FLD
+ }
+
+ void
+ m32rbf_extract_sfmt_ldb_d (m32rbf_scache* abuf, m32rbf_cpu* current_cpu, PCADDR pc, m32rbf_insn_word base_insn, m32rbf_insn_word entire_insn){
+ m32rbf_insn_word insn = entire_insn;
+ #define FLD(f) abuf->fields.sfmt_add3.f
+ UINT f_r1;
+ UINT f_r2;
+ INT f_simm16;
+
+ f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
+ f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
+ f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_simm16) = f_simm16;
+ FLD (f_r2) = f_r2;
+ FLD (f_r1) = f_r1;
+ FLD (i_sr) = & current_cpu->hardware.h_gr[f_r2];
+ FLD (i_dr) = & current_cpu->hardware.h_gr[f_r1];
+ if (UNLIKELY(current_cpu->trace_extract_p))
+ {
+ current_cpu->trace_stream
+ << "0x" << hex << pc << dec << " (sfmt_ldb_d)\t"
+ << " f_simm16:0x" << hex << f_simm16 << dec
+ << " f_r2:0x" << hex << f_r2 << dec
+ << " f_r1:0x" << hex << f_r1 << dec
+ << endl;
+ }
+
+ #undef FLD
+ }
+
+ void
+ m32rbf_extract_sfmt_ldh (m32rbf_scache* abuf, m32rbf_cpu* current_cpu, PCADDR pc, m32rbf_insn_word base_insn, m32rbf_insn_word entire_insn){
+ m32rbf_insn_word insn = entire_insn;
+ #define FLD(f) abuf->fields.sfmt_and3.f
+ UINT f_r1;
+ UINT f_r2;
+
+ f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
+ f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_r2) = f_r2;
+ FLD (f_r1) = f_r1;
+ FLD (i_sr) = & current_cpu->hardware.h_gr[f_r2];
+ FLD (i_dr) = & current_cpu->hardware.h_gr[f_r1];
+ if (UNLIKELY(current_cpu->trace_extract_p))
+ {
+ current_cpu->trace_stream
+ << "0x" << hex << pc << dec << " (sfmt_ldh)\t"
+ << " f_r2:0x" << hex << f_r2 << dec
+ << " f_r1:0x" << hex << f_r1 << dec
+ << endl;
+ }
+
+ #undef FLD
+ }
+
+ void
+ m32rbf_extract_sfmt_ldh_d (m32rbf_scache* abuf, m32rbf_cpu* current_cpu, PCADDR pc, m32rbf_insn_word base_insn, m32rbf_insn_word entire_insn){
+ m32rbf_insn_word insn = entire_insn;
+ #define FLD(f) abuf->fields.sfmt_add3.f
+ UINT f_r1;
+ UINT f_r2;
+ INT f_simm16;
+
+ f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
+ f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
+ f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_simm16) = f_simm16;
+ FLD (f_r2) = f_r2;
+ FLD (f_r1) = f_r1;
+ FLD (i_sr) = & current_cpu->hardware.h_gr[f_r2];
+ FLD (i_dr) = & current_cpu->hardware.h_gr[f_r1];
+ if (UNLIKELY(current_cpu->trace_extract_p))
+ {
+ current_cpu->trace_stream
+ << "0x" << hex << pc << dec << " (sfmt_ldh_d)\t"
<< " f_simm16:0x" << hex << f_simm16 << dec
<< " f_r2:0x" << hex << f_r2 << dec
<< " f_r1:0x" << hex << f_r1 << dec
Index: sid/component/cgen-cpu/m32r/m32r-decode.h
===================================================================
RCS file: /cvs/src/src/sid/component/cgen-cpu/m32r/m32r-decode.h,v
retrieving revision 1.2
diff -c -p -r1.2 m32r-decode.h
*** sid/component/cgen-cpu/m32r/m32r-decode.h 29 Jan 2001 20:03:26 -0000 1.2
--- sid/component/cgen-cpu/m32r/m32r-decode.h 15 Jan 2003 19:55:16 -0000
***************
*** 2,10 ****
THIS FILE IS MACHINE GENERATED WITH CGEN.
! Copyright (C) 2000 Red Hat, Inc.
! This file is part of the Cygnus Simulators.
*/
--- 2,10 ----
THIS FILE IS MACHINE GENERATED WITH CGEN.
! Copyright (C) 2000, 2001 Red Hat, Inc.
! This file is part of the Red Hat simulators.
*/
*************** typedef enum m32rbf_insn_type {
*** 46,52 ****
, M32RBF_INSN_ST_D, M32RBF_INSN_STB, M32RBF_INSN_STB_D, M32RBF_INSN_STH
, M32RBF_INSN_STH_D, M32RBF_INSN_ST_PLUS, M32RBF_INSN_ST_MINUS, M32RBF_INSN_SUB
, M32RBF_INSN_SUBV, M32RBF_INSN_SUBX, M32RBF_INSN_TRAP, M32RBF_INSN_UNLOCK
- , M32RBF_INSN_MAX
} M32RBF_INSN_TYPE;
--- 46,51 ----
Index: sid/component/cgen-cpu/m32r/m32r-defs.h
===================================================================
RCS file: /cvs/src/src/sid/component/cgen-cpu/m32r/m32r-defs.h,v
retrieving revision 1.1
diff -c -p -r1.1 m32r-defs.h
*** sid/component/cgen-cpu/m32r/m32r-defs.h 7 Dec 2000 19:30:49 -0000 1.1
--- sid/component/cgen-cpu/m32r/m32r-defs.h 15 Jan 2003 19:55:16 -0000
***************
*** 2,10 ****
THIS FILE IS MACHINE GENERATED WITH CGEN.
! Copyright (C) 2000 Red Hat, Inc.
! This file is part of the Cygnus Simulators.
*/
--- 2,10 ----
THIS FILE IS MACHINE GENERATED WITH CGEN.
! Copyright (C) 2000, 2001 Red Hat, Inc.
! This file is part of the Red Hat simulators.
*/
Index: sid/component/cgen-cpu/m32r/m32r-desc.h
===================================================================
RCS file: /cvs/src/src/sid/component/cgen-cpu/m32r/m32r-desc.h,v
retrieving revision 1.1
diff -c -p -r1.1 m32r-desc.h
*** sid/component/cgen-cpu/m32r/m32r-desc.h 7 Dec 2000 19:30:49 -0000 1.1
--- sid/component/cgen-cpu/m32r/m32r-desc.h 15 Jan 2003 19:55:16 -0000
***************
*** 2,10 ****
THIS FILE IS MACHINE GENERATED WITH CGEN.
! Copyright (C) 2000 Red Hat, Inc.
! This file is part of the Cygnus Simulators.
*/
--- 2,10 ----
THIS FILE IS MACHINE GENERATED WITH CGEN.
! Copyright (C) 2000, 2001 Red Hat, Inc.
! This file is part of the Red Hat simulators.
*/
*************** struct m32r_insn_attr {
*** 104,109 ****
--- 104,110 ----
inline int get_special_attr () { return (bools & (1<<CGEN_INSN_SPECIAL)) != 0; }
};
+ #define MACH_M32R_INSN_CHUNK_BITSIZE 0
} // end m32r namespace
Index: sid/component/cgen-cpu/m32r/m32r-sem.cxx
===================================================================
RCS file: /cvs/src/src/sid/component/cgen-cpu/m32r/m32r-sem.cxx,v
retrieving revision 1.4
diff -c -p -r1.4 m32r-sem.cxx
*** sid/component/cgen-cpu/m32r/m32r-sem.cxx 1 Mar 2001 19:15:33 -0000 1.4
--- sid/component/cgen-cpu/m32r/m32r-sem.cxx 15 Jan 2003 19:55:16 -0000
***************
*** 2,10 ****
THIS FILE IS MACHINE GENERATED WITH CGEN.
! Copyright (C) 2000 Red Hat, Inc.
! This file is part of the Cygnus Simulators.
*/
--- 2,10 ----
THIS FILE IS MACHINE GENERATED WITH CGEN.
! Copyright (C) 2000, 2001 Red Hat, Inc.
! This file is part of the Red Hat simulators.
*/
Index: sid/component/cgen-cpu/xstormy16/xstormy16-decode.cxx
===================================================================
RCS file: /cvs/src/src/sid/component/cgen-cpu/xstormy16/xstormy16-decode.cxx,v
retrieving revision 1.3
diff -c -p -r1.3 xstormy16-decode.cxx
*** sid/component/cgen-cpu/xstormy16/xstormy16-decode.cxx 25 Nov 2002 21:15:23 -0000 1.3
--- sid/component/cgen-cpu/xstormy16/xstormy16-decode.cxx 15 Jan 2003 19:55:16 -0000
*************** xstormy16_scache::decode (xstormy16_cpu*
*** 431,439 ****
--- 431,447 ----
}
case 6 :
{
+ <<<<<<< xstormy16-decode.cxx
+ unsigned int val = (((insn >> 20) & (1 << 0)));
+ =======
unsigned int val = (((insn >> 20) & (3 << 0)));
+ >>>>>>> 1.3
switch (val)
{
+ <<<<<<< xstormy16-decode.cxx
+ case 0 : itype = XSTORMY16_INSN_DIV; xstormy16_extract_sfmt_mul (this, current_cpu, pc, base_insn, entire_insn); goto done;
+ case 1 : itype = XSTORMY16_INSN_MUL; xstormy16_extract_sfmt_mul (this, current_cpu, pc, base_insn, entire_insn); goto done;
+ =======
case 0 : itype = XSTORMY16_INSN_DIV; xstormy16_extract_sfmt_mul (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 1 : itype = XSTORMY16_INSN_MUL; xstormy16_extract_sfmt_mul (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 2 : itype = XSTORMY16_INSN_DIVLH; xstormy16_extract_sfmt_sdivlh (this, current_cpu, pc, base_insn, entire_insn); goto done;
*************** xstormy16_scache::decode (xstormy16_cpu*
*** 447,452 ****
--- 455,461 ----
{
case 0 : itype = XSTORMY16_INSN_SDIV; xstormy16_extract_sfmt_sdiv (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 1 : itype = XSTORMY16_INSN_SDIVLH; xstormy16_extract_sfmt_sdivlh (this, current_cpu, pc, base_insn, entire_insn); goto done;
+ >>>>>>> 1.3
default : itype = XSTORMY16_INSN_X_INVALID; xstormy16_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
}
}
Index: sid/component/cgen-cpu/xstormy16/xstormy16-decode.h
===================================================================
RCS file: /cvs/src/src/sid/component/cgen-cpu/xstormy16/xstormy16-decode.h,v
retrieving revision 1.2
diff -c -p -r1.2 xstormy16-decode.h
*** sid/component/cgen-cpu/xstormy16/xstormy16-decode.h 20 Nov 2002 03:15:43 -0000 1.2
--- sid/component/cgen-cpu/xstormy16/xstormy16-decode.h 15 Jan 2003 19:55:16 -0000
*************** typedef enum xstormy16_insn_type {
*** 50,58 ****
--- 50,64 ----
, XSTORMY16_INSN_BGR, XSTORMY16_INSN_BR, XSTORMY16_INSN_JMP, XSTORMY16_INSN_JMPF
, XSTORMY16_INSN_CALLRGR, XSTORMY16_INSN_CALLRIMM, XSTORMY16_INSN_CALLGR, XSTORMY16_INSN_CALLFIMM
, XSTORMY16_INSN_ICALLRGR, XSTORMY16_INSN_ICALLGR, XSTORMY16_INSN_ICALLFIMM, XSTORMY16_INSN_IRET
+ <<<<<<< xstormy16-decode.h
+ , XSTORMY16_INSN_RET, XSTORMY16_INSN_MUL, XSTORMY16_INSN_DIV, XSTORMY16_INSN_NOP
+ , XSTORMY16_INSN_HALT, XSTORMY16_INSN_HOLD, XSTORMY16_INSN_HOLDX, XSTORMY16_INSN_BRK
+ , XSTORMY16_INSN_SYSCALL
+ =======
, XSTORMY16_INSN_RET, XSTORMY16_INSN_MUL, XSTORMY16_INSN_DIV, XSTORMY16_INSN_SDIV
, XSTORMY16_INSN_SDIVLH, XSTORMY16_INSN_DIVLH, XSTORMY16_INSN_NOP, XSTORMY16_INSN_HALT
, XSTORMY16_INSN_HOLD, XSTORMY16_INSN_HOLDX, XSTORMY16_INSN_BRK, XSTORMY16_INSN_SYSCALL
+ >>>>>>> 1.2
} XSTORMY16_INSN_TYPE;
Index: sid/component/cgen-cpu/xstormy16/xstormy16-sem.cxx
===================================================================
RCS file: /cvs/src/src/sid/component/cgen-cpu/xstormy16/xstormy16-sem.cxx,v
retrieving revision 1.2
diff -c -p -r1.2 xstormy16-sem.cxx
*** sid/component/cgen-cpu/xstormy16/xstormy16-sem.cxx 20 Nov 2002 03:15:43 -0000 1.2
--- sid/component/cgen-cpu/xstormy16/xstormy16-sem.cxx 15 Jan 2003 19:55:16 -0000
*************** xstormy16_sem_div (xstormy16_cpu* curren
*** 4990,4995 ****
--- 4990,4998 ----
{
SI opval = ORSI (ANDSI (current_cpu->h_gr_get (((UINT) 14)), 65436), ORBI (ORBI (EQHI (ANDHI (tmp_nvalue, 255), 0), SLLHI (EQHI (tmp_nvalue, 0), 1)), ORHI (SLLHI (current_cpu->parity (tmp_nvalue), 5), SLLHI (LTHI (tmp_nvalue, 0), 6))));
current_cpu->h_gr_set (((UINT) 14), opval);
+ <<<<<<< xstormy16-sem.cxx
+ if (UNLIKELY(current_cpu->trace_result_p))
+ =======
if (UNLIKELY(current_cpu->trace_result_p))
current_cpu->trace_stream << "gr" << '[' << ((UINT) 14) << ']' << ":=0x" << hex << opval << dec << " ";
}
*************** xstormy16_sem_divlh (xstormy16_cpu* curr
*** 5118,5123 ****
--- 5121,5127 ----
SI opval = ORSI (ANDSI (current_cpu->h_gr_get (((UINT) 14)), 65436), ORBI (ORBI (EQHI (ANDHI (tmp_nvalue, 255), 0), SLLHI (EQHI (tmp_nvalue, 0), 1)), ORHI (SLLHI (current_cpu->parity (tmp_nvalue), 5), SLLHI (LTHI (tmp_nvalue, 0), 6))));
current_cpu->h_gr_set (((UINT) 14), opval);
if (UNLIKELY(current_cpu->trace_result_p))
+ >>>>>>> 1.2
current_cpu->trace_stream << "gr" << '[' << ((UINT) 14) << ']' << ":=0x" << hex << opval << dec << " ";
}
{
Index: sid/component/cgen-cpu/xstormy16/xstormy16-write.cxx
===================================================================
RCS file: /cvs/src/src/sid/component/cgen-cpu/xstormy16/xstormy16-write.cxx,v
retrieving revision 1.2
diff -c -p -r1.2 xstormy16-write.cxx
*** sid/component/cgen-cpu/xstormy16/xstormy16-write.cxx 20 Nov 2002 03:15:44 -0000 1.2
--- sid/component/cgen-cpu/xstormy16/xstormy16-write.cxx 15 Jan 2003 19:55:16 -0000
*************** This file is part of the Red Hat simulat
*** 11,16 ****
--- 11,1828 ----
#include "xstormy16.h"
+ <<<<<<< xstormy16-write.cxx
+ using namespace xstormy16;
+
+
+ sem_status
+ xstormy16_write_sfmt_empty (xstormy16_cpu* current_cpu, xstormy16_scache* sem, xstormy16_parexec* par_exec)
+ {
+ #define FLD(f) abuf->fields.fmt_empty.f
+ #define OPRND(f) par_exec->operands.sfmt_empty.f
+ xstormy16_scache* abuf = sem;
+ unsigned long long written = abuf->written;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = 0; // dummy value for branches
+ sem_status status = SEM_STATUS_NORMAL; // ditto
+
+
+ return status;
+ #undef OPRND
+ #undef FLD
+ }
+
+
+ sem_status
+ xstormy16_write_sfmt_movlmemimm (xstormy16_cpu* current_cpu, xstormy16_scache* sem, xstormy16_parexec* par_exec)
+ {
+ #define FLD(f) abuf->fields.sfmt_movlmemimm.f
+ #define OPRND(f) par_exec->operands.sfmt_movlmemimm.f
+ xstormy16_scache* abuf = sem;
+ unsigned long long written = abuf->written;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = 0; // dummy value for branches
+ sem_status status = SEM_STATUS_NORMAL; // ditto
+
+ if (written & (1ULL << 5))
+ {
+ current_cpu->SETMEMHI (pc, OPRND (h_memory_HI_lmem8_idx), OPRND (h_memory_HI_lmem8));
+ }
+ if (written & (1ULL << 6))
+ {
+ current_cpu->SETMEMQI (pc, OPRND (h_memory_QI_lmem8_idx), OPRND (h_memory_QI_lmem8));
+ }
+ if (written & (1ULL << 7))
+ {
+ current_cpu->h_gr_set (((UINT) 14), OPRND (psw));
+ }
+
+ return status;
+ #undef OPRND
+ #undef FLD
+ }
+
+
+ sem_status
+ xstormy16_write_sfmt_movhmemimm (xstormy16_cpu* current_cpu, xstormy16_scache* sem, xstormy16_parexec* par_exec)
+ {
+ #define FLD(f) abuf->fields.sfmt_movhmemimm.f
+ #define OPRND(f) par_exec->operands.sfmt_movhmemimm.f
+ xstormy16_scache* abuf = sem;
+ unsigned long long written = abuf->written;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = 0; // dummy value for branches
+ sem_status status = SEM_STATUS_NORMAL; // ditto
+
+ if (written & (1ULL << 5))
+ {
+ current_cpu->SETMEMHI (pc, OPRND (h_memory_HI_hmem8_idx), OPRND (h_memory_HI_hmem8));
+ }
+ if (written & (1ULL << 6))
+ {
+ current_cpu->SETMEMQI (pc, OPRND (h_memory_QI_hmem8_idx), OPRND (h_memory_QI_hmem8));
+ }
+ if (written & (1ULL << 7))
+ {
+ current_cpu->h_gr_set (((UINT) 14), OPRND (psw));
+ }
+
+ return status;
+ #undef OPRND
+ #undef FLD
+ }
+
+
+ sem_status
+ xstormy16_write_sfmt_movlgrmem (xstormy16_cpu* current_cpu, xstormy16_scache* sem, xstormy16_parexec* par_exec)
+ {
+ #define FLD(f) abuf->fields.sfmt_movlgrmem.f
+ #define OPRND(f) par_exec->operands.sfmt_movlgrmem.f
+ xstormy16_scache* abuf = sem;
+ unsigned long long written = abuf->written;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = 0; // dummy value for branches
+ sem_status status = SEM_STATUS_NORMAL; // ditto
+
+ if (written & (1ULL << 7))
+ {
+ current_cpu->h_gr_set (OPRND (h_gr_HI_index_of__DFLT_Rm_idx), OPRND (h_gr_HI_index_of__DFLT_Rm));
+ }
+ if (written & (1ULL << 8))
+ {
+ current_cpu->h_gr_set (((UINT) 14), OPRND (psw));
+ }
+
+ return status;
+ #undef OPRND
+ #undef FLD
+ }
+
+
+ sem_status
+ xstormy16_write_sfmt_movhgrmem (xstormy16_cpu* current_cpu, xstormy16_scache* sem, xstormy16_parexec* par_exec)
+ {
+ #define FLD(f) abuf->fields.sfmt_movhgrmem.f
+ #define OPRND(f) par_exec->operands.sfmt_movhgrmem.f
+ xstormy16_scache* abuf = sem;
+ unsigned long long written = abuf->written;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = 0; // dummy value for branches
+ sem_status status = SEM_STATUS_NORMAL; // ditto
+
+ if (written & (1ULL << 7))
+ {
+ current_cpu->h_gr_set (OPRND (h_gr_HI_index_of__DFLT_Rm_idx), OPRND (h_gr_HI_index_of__DFLT_Rm));
+ }
+ if (written & (1ULL << 8))
+ {
+ current_cpu->h_gr_set (((UINT) 14), OPRND (psw));
+ }
+
+ return status;
+ #undef OPRND
+ #undef FLD
+ }
+
+
+ sem_status
+ xstormy16_write_sfmt_movlmemgr (xstormy16_cpu* current_cpu, xstormy16_scache* sem, xstormy16_parexec* par_exec)
+ {
+ #define FLD(f) abuf->fields.sfmt_movlgrmem.f
+ #define OPRND(f) par_exec->operands.sfmt_movlmemgr.f
+ xstormy16_scache* abuf = sem;
+ unsigned long long written = abuf->written;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = 0; // dummy value for branches
+ sem_status status = SEM_STATUS_NORMAL; // ditto
+
+ if (written & (1ULL << 5))
+ {
+ current_cpu->SETMEMHI (pc, OPRND (h_memory_HI_lmem8_idx), OPRND (h_memory_HI_lmem8));
+ }
+ if (written & (1ULL << 6))
+ {
+ current_cpu->SETMEMQI (pc, OPRND (h_memory_QI_lmem8_idx), OPRND (h_memory_QI_lmem8));
+ }
+ if (written & (1ULL << 7))
+ {
+ current_cpu->h_gr_set (((UINT) 14), OPRND (psw));
+ }
+
+ return status;
+ #undef OPRND
+ #undef FLD
+ }
+
+
+ sem_status
+ xstormy16_write_sfmt_movgrgri (xstormy16_cpu* current_cpu, xstormy16_scache* sem, xstormy16_parexec* par_exec)
+ {
+ #define FLD(f) abuf->fields.sfmt_movfgrgrii.f
+ #define OPRND(f) par_exec->operands.sfmt_movgrgri.f
+ xstormy16_scache* abuf = sem;
+ unsigned long long written = abuf->written;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = 0; // dummy value for branches
+ sem_status status = SEM_STATUS_NORMAL; // ditto
+
+ if (written & (1ULL << 7))
+ {
+ current_cpu->h_gr_set (OPRND (h_gr_HI_index_of__DFLT_Rdm_idx), OPRND (h_gr_HI_index_of__DFLT_Rdm));
+ }
+ if (written & (1ULL << 8))
+ {
+ current_cpu->h_gr_set (((UINT) 14), OPRND (psw));
+ }
+
+ return status;
+ #undef OPRND
+ #undef FLD
+ }
+
+
+ sem_status
+ xstormy16_write_sfmt_movgrgripostinc (xstormy16_cpu* current_cpu, xstormy16_scache* sem, xstormy16_parexec* par_exec)
+ {
+ #define FLD(f) abuf->fields.sfmt_movfgrgrii.f
+ #define OPRND(f) par_exec->operands.sfmt_movgrgripostinc.f
+ xstormy16_scache* abuf = sem;
+ unsigned long long written = abuf->written;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = 0; // dummy value for branches
+ sem_status status = SEM_STATUS_NORMAL; // ditto
+
+ current_cpu->h_gr_set (FLD (f_Rs), OPRND (Rs));
+ if (written & (1ULL << 8))
+ {
+ current_cpu->h_gr_set (OPRND (h_gr_HI_index_of__DFLT_Rdm_idx), OPRND (h_gr_HI_index_of__DFLT_Rdm));
+ }
+ if (written & (1ULL << 9))
+ {
+ current_cpu->h_gr_set (((UINT) 14), OPRND (psw));
+ }
+
+ return status;
+ #undef OPRND
+ #undef FLD
+ }
+
+
+ sem_status
+ xstormy16_write_sfmt_movgrgripredec (xstormy16_cpu* current_cpu, xstormy16_scache* sem, xstormy16_parexec* par_exec)
+ {
+ #define FLD(f) abuf->fields.sfmt_movfgrgrii.f
+ #define OPRND(f) par_exec->operands.sfmt_movgrgripredec.f
+ xstormy16_scache* abuf = sem;
+ unsigned long long written = abuf->written;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = 0; // dummy value for branches
+ sem_status status = SEM_STATUS_NORMAL; // ditto
+
+ current_cpu->h_gr_set (FLD (f_Rs), OPRND (Rs));
+ if (written & (1ULL << 8))
+ {
+ current_cpu->h_gr_set (OPRND (h_gr_HI_index_of__DFLT_Rdm_idx), OPRND (h_gr_HI_index_of__DFLT_Rdm));
+ }
+ if (written & (1ULL << 9))
+ {
+ current_cpu->h_gr_set (((UINT) 14), OPRND (psw));
+ }
+
+ return status;
+ #undef OPRND
+ #undef FLD
+ }
+
+
+ sem_status
+ xstormy16_write_sfmt_movgrigr (xstormy16_cpu* current_cpu, xstormy16_scache* sem, xstormy16_parexec* par_exec)
+ {
+ #define FLD(f) abuf->fields.sfmt_movfgrgrii.f
+ #define OPRND(f) par_exec->operands.sfmt_movgrigr.f
+ xstormy16_scache* abuf = sem;
+ unsigned long long written = abuf->written;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = 0; // dummy value for branches
+ sem_status status = SEM_STATUS_NORMAL; // ditto
+
+ if (written & (1ULL << 5))
+ {
+ current_cpu->SETMEMHI (pc, OPRND (h_memory_HI_nwhere_idx), OPRND (h_memory_HI_nwhere));
+ }
+ if (written & (1ULL << 6))
+ {
+ current_cpu->SETMEMQI (pc, OPRND (h_memory_QI_Rs_idx), OPRND (h_memory_QI_Rs));
+ }
+ current_cpu->h_gr_set (((UINT) 14), OPRND (psw));
+
+ return status;
+ #undef OPRND
+ #undef FLD
+ }
+
+
+ sem_status
+ xstormy16_write_sfmt_movgripostincgr (xstormy16_cpu* current_cpu, xstormy16_scache* sem, xstormy16_parexec* par_exec)
+ {
+ #define FLD(f) abuf->fields.sfmt_movfgrgrii.f
+ #define OPRND(f) par_exec->operands.sfmt_movgripostincgr.f
+ xstormy16_scache* abuf = sem;
+ unsigned long long written = abuf->written;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = 0; // dummy value for branches
+ sem_status status = SEM_STATUS_NORMAL; // ditto
+
+ current_cpu->h_gr_set (OPRND (h_gr_HI_index_of__DFLT_Rs_idx), OPRND (h_gr_HI_index_of__DFLT_Rs));
+ if (written & (1ULL << 6))
+ {
+ current_cpu->SETMEMHI (pc, OPRND (h_memory_HI_nwhere_idx), OPRND (h_memory_HI_nwhere));
+ }
+ if (written & (1ULL << 7))
+ {
+ current_cpu->SETMEMQI (pc, OPRND (h_memory_QI_Rs_idx), OPRND (h_memory_QI_Rs));
+ }
+ current_cpu->h_gr_set (((UINT) 14), OPRND (psw));
+
+ return status;
+ #undef OPRND
+ #undef FLD
+ }
+
+
+ sem_status
+ xstormy16_write_sfmt_movgripredecgr (xstormy16_cpu* current_cpu, xstormy16_scache* sem, xstormy16_parexec* par_exec)
+ {
+ #define FLD(f) abuf->fields.sfmt_movfgrgrii.f
+ #define OPRND(f) par_exec->operands.sfmt_movgripredecgr.f
+ xstormy16_scache* abuf = sem;
+ unsigned long long written = abuf->written;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = 0; // dummy value for branches
+ sem_status status = SEM_STATUS_NORMAL; // ditto
+
+ current_cpu->h_gr_set (OPRND (h_gr_HI_index_of__DFLT_Rs_idx), OPRND (h_gr_HI_index_of__DFLT_Rs));
+ if (written & (1ULL << 6))
+ {
+ current_cpu->SETMEMHI (pc, OPRND (h_memory_HI_nwhere_idx), OPRND (h_memory_HI_nwhere));
+ }
+ if (written & (1ULL << 7))
+ {
+ current_cpu->SETMEMQI (pc, OPRND (h_memory_QI_Rs_idx), OPRND (h_memory_QI_Rs));
+ }
+ current_cpu->h_gr_set (((UINT) 14), OPRND (psw));
+
+ return status;
+ #undef OPRND
+ #undef FLD
+ }
+
+
+ sem_status
+ xstormy16_write_sfmt_movgrgrii (xstormy16_cpu* current_cpu, xstormy16_scache* sem, xstormy16_parexec* par_exec)
+ {
+ #define FLD(f) abuf->fields.sfmt_movfgrgrii.f
+ #define OPRND(f) par_exec->operands.sfmt_movgrgrii.f
+ xstormy16_scache* abuf = sem;
+ unsigned long long written = abuf->written;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = 0; // dummy value for branches
+ sem_status status = SEM_STATUS_NORMAL; // ditto
+
+ if (written & (1ULL << 8))
+ {
+ current_cpu->h_gr_set (OPRND (h_gr_HI_index_of__DFLT_Rdm_idx), OPRND (h_gr_HI_index_of__DFLT_Rdm));
+ }
+ if (written & (1ULL << 9))
+ {
+ current_cpu->h_gr_set (((UINT) 14), OPRND (psw));
+ }
+
+ return status;
+ #undef OPRND
+ #undef FLD
+ }
+
+
+ sem_status
+ xstormy16_write_sfmt_movgrgriipostinc (xstormy16_cpu* current_cpu, xstormy16_scache* sem, xstormy16_parexec* par_exec)
+ {
+ #define FLD(f) abuf->fields.sfmt_movfgrgrii.f
+ #define OPRND(f) par_exec->operands.sfmt_movgrgriipostinc.f
+ xstormy16_scache* abuf = sem;
+ unsigned long long written = abuf->written;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = 0; // dummy value for branches
+ sem_status status = SEM_STATUS_NORMAL; // ditto
+
+ current_cpu->h_gr_set (FLD (f_Rs), OPRND (Rs));
+ if (written & (1ULL << 9))
+ {
+ current_cpu->h_gr_set (OPRND (h_gr_HI_index_of__DFLT_Rdm_idx), OPRND (h_gr_HI_index_of__DFLT_Rdm));
+ }
+ if (written & (1ULL << 10))
+ {
+ current_cpu->h_gr_set (((UINT) 14), OPRND (psw));
+ }
+
+ return status;
+ #undef OPRND
+ #undef FLD
+ }
+
+
+ sem_status
+ xstormy16_write_sfmt_movgrgriipredec (xstormy16_cpu* current_cpu, xstormy16_scache* sem, xstormy16_parexec* par_exec)
+ {
+ #define FLD(f) abuf->fields.sfmt_movfgrgrii.f
+ #define OPRND(f) par_exec->operands.sfmt_movgrgriipredec.f
+ xstormy16_scache* abuf = sem;
+ unsigned long long written = abuf->written;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = 0; // dummy value for branches
+ sem_status status = SEM_STATUS_NORMAL; // ditto
+
+ current_cpu->h_gr_set (FLD (f_Rs), OPRND (Rs));
+ if (written & (1ULL << 9))
+ {
+ current_cpu->h_gr_set (OPRND (h_gr_HI_index_of__DFLT_Rdm_idx), OPRND (h_gr_HI_index_of__DFLT_Rdm));
+ }
+ if (written & (1ULL << 10))
+ {
+ current_cpu->h_gr_set (((UINT) 14), OPRND (psw));
+ }
+
+ return status;
+ #undef OPRND
+ #undef FLD
+ }
+
+
+ sem_status
+ xstormy16_write_sfmt_movgriigr (xstormy16_cpu* current_cpu, xstormy16_scache* sem, xstormy16_parexec* par_exec)
+ {
+ #define FLD(f) abuf->fields.sfmt_movfgrgrii.f
+ #define OPRND(f) par_exec->operands.sfmt_movgriigr.f
+ xstormy16_scache* abuf = sem;
+ unsigned long long written = abuf->written;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = 0; // dummy value for branches
+ sem_status status = SEM_STATUS_NORMAL; // ditto
+
+ current_cpu->h_gr_set (OPRND (h_gr_HI_index_of__DFLT_Rs_idx), OPRND (h_gr_HI_index_of__DFLT_Rs));
+ if (written & (1ULL << 7))
+ {
+ current_cpu->SETMEMHI (pc, OPRND (h_memory_HI_nwhere_idx), OPRND (h_memory_HI_nwhere));
+ }
+ if (written & (1ULL << 8))
+ {
+ current_cpu->SETMEMQI (pc, OPRND (h_memory_QI_add__DFLT_Rs_imm12_idx), OPRND (h_memory_QI_add__DFLT_Rs_imm12));
+ }
+ current_cpu->h_gr_set (((UINT) 14), OPRND (psw));
+
+ return status;
+ #undef OPRND
+ #undef FLD
+ }
+
+
+ sem_status
+ xstormy16_write_sfmt_movgriipredecgr (xstormy16_cpu* current_cpu, xstormy16_scache* sem, xstormy16_parexec* par_exec)
+ {
+ #define FLD(f) abuf->fields.sfmt_movfgrgrii.f
+ #define OPRND(f) par_exec->operands.sfmt_movgriipredecgr.f
+ xstormy16_scache* abuf = sem;
+ unsigned long long written = abuf->written;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = 0; // dummy value for branches
+ sem_status status = SEM_STATUS_NORMAL; // ditto
+
+ current_cpu->h_gr_set (OPRND (h_gr_HI_index_of__DFLT_Rs_idx), OPRND (h_gr_HI_index_of__DFLT_Rs));
+ if (written & (1ULL << 7))
+ {
+ current_cpu->SETMEMHI (pc, OPRND (h_memory_HI_nwhere_idx), OPRND (h_memory_HI_nwhere));
+ }
+ if (written & (1ULL << 8))
+ {
+ current_cpu->SETMEMQI (pc, OPRND (h_memory_QI_add__DFLT_Rs_imm12_idx), OPRND (h_memory_QI_add__DFLT_Rs_imm12));
+ }
+ current_cpu->h_gr_set (((UINT) 14), OPRND (psw));
+
+ return status;
+ #undef OPRND
+ #undef FLD
+ }
+
+
+ sem_status
+ xstormy16_write_sfmt_movgrgr (xstormy16_cpu* current_cpu, xstormy16_scache* sem, xstormy16_parexec* par_exec)
+ {
+ #define FLD(f) abuf->fields.sfmt_bccgrgr.f
+ #define OPRND(f) par_exec->operands.sfmt_movgrgr.f
+ xstormy16_scache* abuf = sem;
+ unsigned long long written = abuf->written;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = 0; // dummy value for branches
+ sem_status status = SEM_STATUS_NORMAL; // ditto
+
+ current_cpu->h_gr_set (OPRND (h_gr_HI_index_of__DFLT_Rd_idx), OPRND (h_gr_HI_index_of__DFLT_Rd));
+ current_cpu->h_gr_set (((UINT) 14), OPRND (psw));
+
+ return status;
+ #undef OPRND
+ #undef FLD
+ }
+
+
+ sem_status
+ xstormy16_write_sfmt_movwimm8 (xstormy16_cpu* current_cpu, xstormy16_scache* sem, xstormy16_parexec* par_exec)
+ {
+ #define FLD(f) abuf->fields.sfmt_bccgrimm8.f
+ #define OPRND(f) par_exec->operands.sfmt_movwimm8.f
+ xstormy16_scache* abuf = sem;
+ unsigned long long written = abuf->written;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = 0; // dummy value for branches
+ sem_status status = SEM_STATUS_NORMAL; // ditto
+
+ current_cpu->h_gr_set (OPRND (h_gr_HI_Rpsw_idx), OPRND (h_gr_HI_Rpsw));
+ current_cpu->h_gr_set (((UINT) 14), OPRND (psw));
+
+ return status;
+ #undef OPRND
+ #undef FLD
+ }
+
+
+ sem_status
+ xstormy16_write_sfmt_movwgrimm8 (xstormy16_cpu* current_cpu, xstormy16_scache* sem, xstormy16_parexec* par_exec)
+ {
+ #define FLD(f) abuf->fields.sfmt_bccgrimm8.f
+ #define OPRND(f) par_exec->operands.sfmt_movwgrimm8.f
+ xstormy16_scache* abuf = sem;
+ unsigned long long written = abuf->written;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = 0; // dummy value for branches
+ sem_status status = SEM_STATUS_NORMAL; // ditto
+
+ current_cpu->h_gr_set (OPRND (h_gr_HI_index_of__DFLT_Rm_idx), OPRND (h_gr_HI_index_of__DFLT_Rm));
+ current_cpu->h_gr_set (((UINT) 14), OPRND (psw));
+
+ return status;
+ #undef OPRND
+ #undef FLD
+ }
+
+
+ sem_status
+ xstormy16_write_sfmt_movwgrimm16 (xstormy16_cpu* current_cpu, xstormy16_scache* sem, xstormy16_parexec* par_exec)
+ {
+ #define FLD(f) abuf->fields.sfmt_movwgrimm16.f
+ #define OPRND(f) par_exec->operands.sfmt_movwgrimm16.f
+ xstormy16_scache* abuf = sem;
+ unsigned long long written = abuf->written;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = 0; // dummy value for branches
+ sem_status status = SEM_STATUS_NORMAL; // ditto
+
+ current_cpu->h_gr_set (OPRND (h_gr_HI_index_of__DFLT_Rd_idx), OPRND (h_gr_HI_index_of__DFLT_Rd));
+ current_cpu->h_gr_set (((UINT) 14), OPRND (psw));
+
+ return status;
+ #undef OPRND
+ #undef FLD
+ }
+
+
+ sem_status
+ xstormy16_write_sfmt_movlowgr (xstormy16_cpu* current_cpu, xstormy16_scache* sem, xstormy16_parexec* par_exec)
+ {
+ #define FLD(f) abuf->fields.sfmt_jmp.f
+ #define OPRND(f) par_exec->operands.sfmt_movlowgr.f
+ xstormy16_scache* abuf = sem;
+ unsigned long long written = abuf->written;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = 0; // dummy value for branches
+ sem_status status = SEM_STATUS_NORMAL; // ditto
+
+ current_cpu->h_gr_set (OPRND (h_gr_HI_index_of__DFLT_Rd_idx), OPRND (h_gr_HI_index_of__DFLT_Rd));
+ current_cpu->h_gr_set (((UINT) 14), OPRND (psw));
+
+ return status;
+ #undef OPRND
+ #undef FLD
+ }
+
+
+ sem_status
+ xstormy16_write_sfmt_movfgrgri (xstormy16_cpu* current_cpu, xstormy16_scache* sem, xstormy16_parexec* par_exec)
+ {
+ #define FLD(f) abuf->fields.sfmt_movfgrgrii.f
+ #define OPRND(f) par_exec->operands.sfmt_movfgrgri.f
+ xstormy16_scache* abuf = sem;
+ unsigned long long written = abuf->written;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = 0; // dummy value for branches
+ sem_status status = SEM_STATUS_NORMAL; // ditto
+
+ if (written & (1ULL << 8))
+ {
+ current_cpu->h_gr_set (OPRND (h_gr_HI_index_of__DFLT_Rdm_idx), OPRND (h_gr_HI_index_of__DFLT_Rdm));
+ }
+ if (written & (1ULL << 9))
+ {
+ current_cpu->h_gr_set (((UINT) 14), OPRND (psw));
+ }
+
+ return status;
+ #undef OPRND
+ #undef FLD
+ }
+
+
+ sem_status
+ xstormy16_write_sfmt_movfgrgripostinc (xstormy16_cpu* current_cpu, xstormy16_scache* sem, xstormy16_parexec* par_exec)
+ {
+ #define FLD(f) abuf->fields.sfmt_movfgrgrii.f
+ #define OPRND(f) par_exec->operands.sfmt_movfgrgripostinc.f
+ xstormy16_scache* abuf = sem;
+ unsigned long long written = abuf->written;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = 0; // dummy value for branches
+ sem_status status = SEM_STATUS_NORMAL; // ditto
+
+ current_cpu->h_gr_set (FLD (f_Rs), OPRND (Rs));
+ if (written & (1ULL << 9))
+ {
+ current_cpu->h_gr_set (OPRND (h_gr_HI_index_of__DFLT_Rdm_idx), OPRND (h_gr_HI_index_of__DFLT_Rdm));
+ }
+ if (written & (1ULL << 10))
+ {
+ current_cpu->h_gr_set (((UINT) 14), OPRND (psw));
+ }
+
+ return status;
+ #undef OPRND
+ #undef FLD
+ }
+
+
+ sem_status
+ xstormy16_write_sfmt_movfgrgripredec (xstormy16_cpu* current_cpu, xstormy16_scache* sem, xstormy16_parexec* par_exec)
+ {
+ #define FLD(f) abuf->fields.sfmt_movfgrgrii.f
+ #define OPRND(f) par_exec->operands.sfmt_movfgrgripredec.f
+ xstormy16_scache* abuf = sem;
+ unsigned long long written = abuf->written;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = 0; // dummy value for branches
+ sem_status status = SEM_STATUS_NORMAL; // ditto
+
+ current_cpu->h_gr_set (FLD (f_Rs), OPRND (Rs));
+ if (written & (1ULL << 9))
+ {
+ current_cpu->h_gr_set (OPRND (h_gr_HI_index_of__DFLT_Rdm_idx), OPRND (h_gr_HI_index_of__DFLT_Rdm));
+ }
+ if (written & (1ULL << 10))
+ {
+ current_cpu->h_gr_set (((UINT) 14), OPRND (psw));
+ }
+
+ return status;
+ #undef OPRND
+ #undef FLD
+ }
+
+
+ sem_status
+ xstormy16_write_sfmt_movfgrigr (xstormy16_cpu* current_cpu, xstormy16_scache* sem, xstormy16_parexec* par_exec)
+ {
+ #define FLD(f) abuf->fields.sfmt_movfgrgrii.f
+ #define OPRND(f) par_exec->operands.sfmt_movfgrigr.f
+ xstormy16_scache* abuf = sem;
+ unsigned long long written = abuf->written;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = 0; // dummy value for branches
+ sem_status status = SEM_STATUS_NORMAL; // ditto
+
+ if (written & (1ULL << 9))
+ {
+ current_cpu->h_gr_set (OPRND (h_gr_HI_index_of__DFLT_Rs_idx), OPRND (h_gr_HI_index_of__DFLT_Rs));
+ }
+ if (written & (1ULL << 10))
+ {
+ current_cpu->h_gr_set (((UINT) 14), OPRND (psw));
+ }
+
+ return status;
+ #undef OPRND
+ #undef FLD
+ }
+
+
+ sem_status
+ xstormy16_write_sfmt_movfgripredecgr (xstormy16_cpu* current_cpu, xstormy16_scache* sem, xstormy16_parexec* par_exec)
+ {
+ #define FLD(f) abuf->fields.sfmt_movfgrgrii.f
+ #define OPRND(f) par_exec->operands.sfmt_movfgripredecgr.f
+ xstormy16_scache* abuf = sem;
+ unsigned long long written = abuf->written;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = 0; // dummy value for branches
+ sem_status status = SEM_STATUS_NORMAL; // ditto
+
+ current_cpu->h_gr_set (OPRND (h_gr_HI_index_of__DFLT_Rs_idx), OPRND (h_gr_HI_index_of__DFLT_Rs));
+ current_cpu->h_gr_set (((UINT) 14), OPRND (psw));
+
+ return status;
+ #undef OPRND
+ #undef FLD
+ }
+
+
+ sem_status
+ xstormy16_write_sfmt_movfgrgrii (xstormy16_cpu* current_cpu, xstormy16_scache* sem, xstormy16_parexec* par_exec)
+ {
+ #define FLD(f) abuf->fields.sfmt_movfgrgrii.f
+ #define OPRND(f) par_exec->operands.sfmt_movfgrgrii.f
+ xstormy16_scache* abuf = sem;
+ unsigned long long written = abuf->written;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = 0; // dummy value for branches
+ sem_status status = SEM_STATUS_NORMAL; // ditto
+
+ if (written & (1ULL << 9))
+ {
+ current_cpu->h_gr_set (OPRND (h_gr_HI_index_of__DFLT_Rdm_idx), OPRND (h_gr_HI_index_of__DFLT_Rdm));
+ }
+ if (written & (1ULL << 10))
+ {
+ current_cpu->h_gr_set (((UINT) 14), OPRND (psw));
+ }
+
+ return status;
+ #undef OPRND
+ #undef FLD
+ }
+
+
+ sem_status
+ xstormy16_write_sfmt_movfgrgriipostinc (xstormy16_cpu* current_cpu, xstormy16_scache* sem, xstormy16_parexec* par_exec)
+ {
+ #define FLD(f) abuf->fields.sfmt_movfgrgrii.f
+ #define OPRND(f) par_exec->operands.sfmt_movfgrgriipostinc.f
+ xstormy16_scache* abuf = sem;
+ unsigned long long written = abuf->written;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = 0; // dummy value for branches
+ sem_status status = SEM_STATUS_NORMAL; // ditto
+
+ current_cpu->h_gr_set (FLD (f_Rs), OPRND (Rs));
+ if (written & (1ULL << 10))
+ {
+ current_cpu->h_gr_set (OPRND (h_gr_HI_index_of__DFLT_Rdm_idx), OPRND (h_gr_HI_index_of__DFLT_Rdm));
+ }
+ if (written & (1ULL << 11))
+ {
+ current_cpu->h_gr_set (((UINT) 14), OPRND (psw));
+ }
+
+ return status;
+ #undef OPRND
+ #undef FLD
+ }
+
+
+ sem_status
+ xstormy16_write_sfmt_movfgrgriipredec (xstormy16_cpu* current_cpu, xstormy16_scache* sem, xstormy16_parexec* par_exec)
+ {
+ #define FLD(f) abuf->fields.sfmt_movfgrgrii.f
+ #define OPRND(f) par_exec->operands.sfmt_movfgrgriipredec.f
+ xstormy16_scache* abuf = sem;
+ unsigned long long written = abuf->written;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = 0; // dummy value for branches
+ sem_status status = SEM_STATUS_NORMAL; // ditto
+
+ current_cpu->h_gr_set (FLD (f_Rs), OPRND (Rs));
+ if (written & (1ULL << 10))
+ {
+ current_cpu->h_gr_set (OPRND (h_gr_HI_index_of__DFLT_Rdm_idx), OPRND (h_gr_HI_index_of__DFLT_Rdm));
+ }
+ if (written & (1ULL << 11))
+ {
+ current_cpu->h_gr_set (((UINT) 14), OPRND (psw));
+ }
+
+ return status;
+ #undef OPRND
+ #undef FLD
+ }
+
+
+ sem_status
+ xstormy16_write_sfmt_movfgriigr (xstormy16_cpu* current_cpu, xstormy16_scache* sem, xstormy16_parexec* par_exec)
+ {
+ #define FLD(f) abuf->fields.sfmt_movfgrgrii.f
+ #define OPRND(f) par_exec->operands.sfmt_movfgriigr.f
+ xstormy16_scache* abuf = sem;
+ unsigned long long written = abuf->written;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = 0; // dummy value for branches
+ sem_status status = SEM_STATUS_NORMAL; // ditto
+
+ current_cpu->h_gr_set (OPRND (h_gr_HI_index_of__DFLT_Rs_idx), OPRND (h_gr_HI_index_of__DFLT_Rs));
+ if (written & (1ULL << 8))
+ {
+ current_cpu->SETMEMHI (pc, OPRND (h_memory_HI_and__DFLT_add__DFLT_join__SI_HI_Rb_Rs_imm12_4294967294_idx), OPRND (h_memory_HI_and__DFLT_add__DFLT_join__SI_HI_Rb_Rs_imm12_4294967294));
+ }
+ if (written & (1ULL << 9))
+ {
+ current_cpu->SETMEMQI (pc, OPRND (h_memory_QI_add__DFLT_join__SI_HI_Rb_Rs_imm12_idx), OPRND (h_memory_QI_add__DFLT_join__SI_HI_Rb_Rs_imm12));
+ }
+ current_cpu->h_gr_set (((UINT) 14), OPRND (psw));
+
+ return status;
+ #undef OPRND
+ #undef FLD
+ }
+
+
+ sem_status
+ xstormy16_write_sfmt_movfgriipredecgr (xstormy16_cpu* current_cpu, xstormy16_scache* sem, xstormy16_parexec* par_exec)
+ {
+ #define FLD(f) abuf->fields.sfmt_movfgrgrii.f
+ #define OPRND(f) par_exec->operands.sfmt_movfgriipredecgr.f
+ xstormy16_scache* abuf = sem;
+ unsigned long long written = abuf->written;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = 0; // dummy value for branches
+ sem_status status = SEM_STATUS_NORMAL; // ditto
+
+ current_cpu->h_gr_set (OPRND (h_gr_HI_index_of__DFLT_Rs_idx), OPRND (h_gr_HI_index_of__DFLT_Rs));
+ if (written & (1ULL << 8))
+ {
+ current_cpu->SETMEMHI (pc, OPRND (h_memory_HI_and__DFLT_add__DFLT_join__SI_HI_Rb_Rs_imm12_4294967294_idx), OPRND (h_memory_HI_and__DFLT_add__DFLT_join__SI_HI_Rb_Rs_imm12_4294967294));
+ }
+ if (written & (1ULL << 9))
+ {
+ current_cpu->SETMEMQI (pc, OPRND (h_memory_QI_add__DFLT_join__SI_HI_Rb_Rs_imm12_idx), OPRND (h_memory_QI_add__DFLT_join__SI_HI_Rb_Rs_imm12));
+ }
+ current_cpu->h_gr_set (((UINT) 14), OPRND (psw));
+
+ return status;
+ #undef OPRND
+ #undef FLD
+ }
+
+
+ sem_status
+ xstormy16_write_sfmt_maskgrgr (xstormy16_cpu* current_cpu, xstormy16_scache* sem, xstormy16_parexec* par_exec)
+ {
+ #define FLD(f) abuf->fields.sfmt_bccgrgr.f
+ #define OPRND(f) par_exec->operands.sfmt_maskgrgr.f
+ xstormy16_scache* abuf = sem;
+ unsigned long long written = abuf->written;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = 0; // dummy value for branches
+ sem_status status = SEM_STATUS_NORMAL; // ditto
+
+ current_cpu->h_gr_set (OPRND (h_gr_HI_index_of__DFLT_Rd_idx), OPRND (h_gr_HI_index_of__DFLT_Rd));
+ current_cpu->h_gr_set (((UINT) 14), OPRND (psw));
+
+ return status;
+ #undef OPRND
+ #undef FLD
+ }
+
+
+ sem_status
+ xstormy16_write_sfmt_maskgrimm16 (xstormy16_cpu* current_cpu, xstormy16_scache* sem, xstormy16_parexec* par_exec)
+ {
+ #define FLD(f) abuf->fields.sfmt_movwgrimm16.f
+ #define OPRND(f) par_exec->operands.sfmt_maskgrimm16.f
+ xstormy16_scache* abuf = sem;
+ unsigned long long written = abuf->written;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = 0; // dummy value for branches
+ sem_status status = SEM_STATUS_NORMAL; // ditto
+
+ current_cpu->h_gr_set (OPRND (h_gr_HI_index_of__DFLT_Rd_idx), OPRND (h_gr_HI_index_of__DFLT_Rd));
+ current_cpu->h_gr_set (((UINT) 14), OPRND (psw));
+
+ return status;
+ #undef OPRND
+ #undef FLD
+ }
+
+
+ sem_status
+ xstormy16_write_sfmt_pushgr (xstormy16_cpu* current_cpu, xstormy16_scache* sem, xstormy16_parexec* par_exec)
+ {
+ #define FLD(f) abuf->fields.sfmt_jmp.f
+ #define OPRND(f) par_exec->operands.sfmt_pushgr.f
+ xstormy16_scache* abuf = sem;
+ unsigned long long written = abuf->written;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = 0; // dummy value for branches
+ sem_status status = SEM_STATUS_NORMAL; // ditto
+
+ current_cpu->SETMEMHI (pc, OPRND (h_memory_HI_sp_idx), OPRND (h_memory_HI_sp));
+ current_cpu->h_gr_set (((UINT) 15), OPRND (sp));
+
+ return status;
+ #undef OPRND
+ #undef FLD
+ }
+
+
+ sem_status
+ xstormy16_write_sfmt_popgr (xstormy16_cpu* current_cpu, xstormy16_scache* sem, xstormy16_parexec* par_exec)
+ {
+ #define FLD(f) abuf->fields.sfmt_jmp.f
+ #define OPRND(f) par_exec->operands.sfmt_popgr.f
+ xstormy16_scache* abuf = sem;
+ unsigned long long written = abuf->written;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = 0; // dummy value for branches
+ sem_status status = SEM_STATUS_NORMAL; // ditto
+
+ current_cpu->h_gr_set (FLD (f_Rd), OPRND (Rd));
+ current_cpu->h_gr_set (((UINT) 15), OPRND (sp));
+
+ return status;
+ #undef OPRND
+ #undef FLD
+ }
+
+
+ sem_status
+ xstormy16_write_sfmt_swpn (xstormy16_cpu* current_cpu, xstormy16_scache* sem, xstormy16_parexec* par_exec)
+ {
+ #define FLD(f) abuf->fields.sfmt_jmp.f
+ #define OPRND(f) par_exec->operands.sfmt_swpn.f
+ xstormy16_scache* abuf = sem;
+ unsigned long long written = abuf->written;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = 0; // dummy value for branches
+ sem_status status = SEM_STATUS_NORMAL; // ditto
+
+ current_cpu->h_gr_set (OPRND (h_gr_HI_index_of__DFLT_Rd_idx), OPRND (h_gr_HI_index_of__DFLT_Rd));
+ current_cpu->h_gr_set (((UINT) 14), OPRND (psw));
+
+ return status;
+ #undef OPRND
+ #undef FLD
+ }
+
+
+ sem_status
+ xstormy16_write_sfmt_swpw (xstormy16_cpu* current_cpu, xstormy16_scache* sem, xstormy16_parexec* par_exec)
+ {
+ #define FLD(f) abuf->fields.sfmt_bccgrgr.f
+ #define OPRND(f) par_exec->operands.sfmt_swpw.f
+ xstormy16_scache* abuf = sem;
+ unsigned long long written = abuf->written;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = 0; // dummy value for branches
+ sem_status status = SEM_STATUS_NORMAL; // ditto
+
+ current_cpu->h_gr_set (FLD (f_Rs), OPRND (Rs));
+ current_cpu->h_gr_set (OPRND (h_gr_HI_index_of__DFLT_Rd_idx), OPRND (h_gr_HI_index_of__DFLT_Rd));
+ current_cpu->h_gr_set (((UINT) 14), OPRND (psw));
+
+ return status;
+ #undef OPRND
+ #undef FLD
+ }
+
+
+ sem_status
+ xstormy16_write_sfmt_andgrgr (xstormy16_cpu* current_cpu, xstormy16_scache* sem, xstormy16_parexec* par_exec)
+ {
+ #define FLD(f) abuf->fields.sfmt_bccgrgr.f
+ #define OPRND(f) par_exec->operands.sfmt_andgrgr.f
+ xstormy16_scache* abuf = sem;
+ unsigned long long written = abuf->written;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = 0; // dummy value for branches
+ sem_status status = SEM_STATUS_NORMAL; // ditto
+
+ current_cpu->h_gr_set (OPRND (h_gr_HI_index_of__DFLT_Rd_idx), OPRND (h_gr_HI_index_of__DFLT_Rd));
+ current_cpu->h_gr_set (((UINT) 14), OPRND (psw));
+
+ return status;
+ #undef OPRND
+ #undef FLD
+ }
+
+
+ sem_status
+ xstormy16_write_sfmt_andimm8 (xstormy16_cpu* current_cpu, xstormy16_scache* sem, xstormy16_parexec* par_exec)
+ {
+ #define FLD(f) abuf->fields.sfmt_bccgrimm8.f
+ #define OPRND(f) par_exec->operands.sfmt_andimm8.f
+ xstormy16_scache* abuf = sem;
+ unsigned long long written = abuf->written;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = 0; // dummy value for branches
+ sem_status status = SEM_STATUS_NORMAL; // ditto
+
+ current_cpu->h_gr_set (OPRND (h_gr_HI_Rpsw_idx), OPRND (h_gr_HI_Rpsw));
+ current_cpu->h_gr_set (((UINT) 14), OPRND (psw));
+
+ return status;
+ #undef OPRND
+ #undef FLD
+ }
+
+
+ sem_status
+ xstormy16_write_sfmt_andgrimm16 (xstormy16_cpu* current_cpu, xstormy16_scache* sem, xstormy16_parexec* par_exec)
+ {
+ #define FLD(f) abuf->fields.sfmt_movwgrimm16.f
+ #define OPRND(f) par_exec->operands.sfmt_andgrimm16.f
+ xstormy16_scache* abuf = sem;
+ unsigned long long written = abuf->written;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = 0; // dummy value for branches
+ sem_status status = SEM_STATUS_NORMAL; // ditto
+
+ current_cpu->h_gr_set (OPRND (h_gr_HI_index_of__DFLT_Rd_idx), OPRND (h_gr_HI_index_of__DFLT_Rd));
+ current_cpu->h_gr_set (((UINT) 14), OPRND (psw));
+
+ return status;
+ #undef OPRND
+ #undef FLD
+ }
+
+
+ sem_status
+ xstormy16_write_sfmt_addgrgr (xstormy16_cpu* current_cpu, xstormy16_scache* sem, xstormy16_parexec* par_exec)
+ {
+ #define FLD(f) abuf->fields.sfmt_bccgrgr.f
+ #define OPRND(f) par_exec->operands.sfmt_addgrgr.f
+ xstormy16_scache* abuf = sem;
+ unsigned long long written = abuf->written;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = 0; // dummy value for branches
+ sem_status status = SEM_STATUS_NORMAL; // ditto
+
+ current_cpu->h_gr_set (OPRND (h_gr_HI_index_of__DFLT_Rd_idx), OPRND (h_gr_HI_index_of__DFLT_Rd));
+ current_cpu->h_gr_set (((UINT) 14), OPRND (psw));
+
+ return status;
+ #undef OPRND
+ #undef FLD
+ }
+
+
+ sem_status
+ xstormy16_write_sfmt_addgrimm4 (xstormy16_cpu* current_cpu, xstormy16_scache* sem, xstormy16_parexec* par_exec)
+ {
+ #define FLD(f) abuf->fields.sfmt_bngrimm4.f
+ #define OPRND(f) par_exec->operands.sfmt_addgrimm4.f
+ xstormy16_scache* abuf = sem;
+ unsigned long long written = abuf->written;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = 0; // dummy value for branches
+ sem_status status = SEM_STATUS_NORMAL; // ditto
+
+ current_cpu->h_gr_set (OPRND (h_gr_HI_index_of__DFLT_Rd_idx), OPRND (h_gr_HI_index_of__DFLT_Rd));
+ current_cpu->h_gr_set (((UINT) 14), OPRND (psw));
+
+ return status;
+ #undef OPRND
+ #undef FLD
+ }
+
+
+ sem_status
+ xstormy16_write_sfmt_addimm8 (xstormy16_cpu* current_cpu, xstormy16_scache* sem, xstormy16_parexec* par_exec)
+ {
+ #define FLD(f) abuf->fields.sfmt_bccgrimm8.f
+ #define OPRND(f) par_exec->operands.sfmt_addimm8.f
+ xstormy16_scache* abuf = sem;
+ unsigned long long written = abuf->written;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = 0; // dummy value for branches
+ sem_status status = SEM_STATUS_NORMAL; // ditto
+
+ current_cpu->h_gr_set (OPRND (h_gr_HI_Rpsw_idx), OPRND (h_gr_HI_Rpsw));
+ current_cpu->h_gr_set (((UINT) 14), OPRND (psw));
+
+ return status;
+ #undef OPRND
+ #undef FLD
+ }
+
+
+ sem_status
+ xstormy16_write_sfmt_addgrimm16 (xstormy16_cpu* current_cpu, xstormy16_scache* sem, xstormy16_parexec* par_exec)
+ {
+ #define FLD(f) abuf->fields.sfmt_movwgrimm16.f
+ #define OPRND(f) par_exec->operands.sfmt_addgrimm16.f
+ xstormy16_scache* abuf = sem;
+ unsigned long long written = abuf->written;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = 0; // dummy value for branches
+ sem_status status = SEM_STATUS_NORMAL; // ditto
+
+ current_cpu->h_gr_set (OPRND (h_gr_HI_index_of__DFLT_Rd_idx), OPRND (h_gr_HI_index_of__DFLT_Rd));
+ current_cpu->h_gr_set (((UINT) 14), OPRND (psw));
+
+ return status;
+ #undef OPRND
+ #undef FLD
+ }
+
+
+ sem_status
+ xstormy16_write_sfmt_adcgrgr (xstormy16_cpu* current_cpu, xstormy16_scache* sem, xstormy16_parexec* par_exec)
+ {
+ #define FLD(f) abuf->fields.sfmt_bccgrgr.f
+ #define OPRND(f) par_exec->operands.sfmt_adcgrgr.f
+ xstormy16_scache* abuf = sem;
+ unsigned long long written = abuf->written;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = 0; // dummy value for branches
+ sem_status status = SEM_STATUS_NORMAL; // ditto
+
+ current_cpu->h_gr_set (OPRND (h_gr_HI_index_of__DFLT_Rd_idx), OPRND (h_gr_HI_index_of__DFLT_Rd));
+ current_cpu->h_gr_set (((UINT) 14), OPRND (psw));
+
+ return status;
+ #undef OPRND
+ #undef FLD
+ }
+
+
+ sem_status
+ xstormy16_write_sfmt_adcgrimm4 (xstormy16_cpu* current_cpu, xstormy16_scache* sem, xstormy16_parexec* par_exec)
+ {
+ #define FLD(f) abuf->fields.sfmt_bngrimm4.f
+ #define OPRND(f) par_exec->operands.sfmt_adcgrimm4.f
+ xstormy16_scache* abuf = sem;
+ unsigned long long written = abuf->written;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = 0; // dummy value for branches
+ sem_status status = SEM_STATUS_NORMAL; // ditto
+
+ current_cpu->h_gr_set (OPRND (h_gr_HI_index_of__DFLT_Rd_idx), OPRND (h_gr_HI_index_of__DFLT_Rd));
+ current_cpu->h_gr_set (((UINT) 14), OPRND (psw));
+
+ return status;
+ #undef OPRND
+ #undef FLD
+ }
+
+
+ sem_status
+ xstormy16_write_sfmt_adcimm8 (xstormy16_cpu* current_cpu, xstormy16_scache* sem, xstormy16_parexec* par_exec)
+ {
+ #define FLD(f) abuf->fields.sfmt_bccgrimm8.f
+ #define OPRND(f) par_exec->operands.sfmt_adcimm8.f
+ xstormy16_scache* abuf = sem;
+ unsigned long long written = abuf->written;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = 0; // dummy value for branches
+ sem_status status = SEM_STATUS_NORMAL; // ditto
+
+ current_cpu->h_gr_set (OPRND (h_gr_HI_Rpsw_idx), OPRND (h_gr_HI_Rpsw));
+ current_cpu->h_gr_set (((UINT) 14), OPRND (psw));
+
+ return status;
+ #undef OPRND
+ #undef FLD
+ }
+
+
+ sem_status
+ xstormy16_write_sfmt_adcgrimm16 (xstormy16_cpu* current_cpu, xstormy16_scache* sem, xstormy16_parexec* par_exec)
+ {
+ #define FLD(f) abuf->fields.sfmt_movwgrimm16.f
+ #define OPRND(f) par_exec->operands.sfmt_adcgrimm16.f
+ xstormy16_scache* abuf = sem;
+ unsigned long long written = abuf->written;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = 0; // dummy value for branches
+ sem_status status = SEM_STATUS_NORMAL; // ditto
+
+ current_cpu->h_gr_set (OPRND (h_gr_HI_index_of__DFLT_Rd_idx), OPRND (h_gr_HI_index_of__DFLT_Rd));
+ current_cpu->h_gr_set (((UINT) 14), OPRND (psw));
+
+ return status;
+ #undef OPRND
+ #undef FLD
+ }
+
+
+ sem_status
+ xstormy16_write_sfmt_incgrimm2 (xstormy16_cpu* current_cpu, xstormy16_scache* sem, xstormy16_parexec* par_exec)
+ {
+ #define FLD(f) abuf->fields.sfmt_incgrimm2.f
+ #define OPRND(f) par_exec->operands.sfmt_incgrimm2.f
+ xstormy16_scache* abuf = sem;
+ unsigned long long written = abuf->written;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = 0; // dummy value for branches
+ sem_status status = SEM_STATUS_NORMAL; // ditto
+
+ current_cpu->h_gr_set (OPRND (h_gr_HI_index_of__DFLT_Rd_idx), OPRND (h_gr_HI_index_of__DFLT_Rd));
+ current_cpu->h_gr_set (((UINT) 14), OPRND (psw));
+
+ return status;
+ #undef OPRND
+ #undef FLD
+ }
+
+
+ sem_status
+ xstormy16_write_sfmt_rrcgrgr (xstormy16_cpu* current_cpu, xstormy16_scache* sem, xstormy16_parexec* par_exec)
+ {
+ #define FLD(f) abuf->fields.sfmt_bccgrgr.f
+ #define OPRND(f) par_exec->operands.sfmt_rrcgrgr.f
+ xstormy16_scache* abuf = sem;
+ unsigned long long written = abuf->written;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = 0; // dummy value for branches
+ sem_status status = SEM_STATUS_NORMAL; // ditto
+
+ current_cpu->h_gr_set (OPRND (h_gr_HI_index_of__DFLT_Rd_idx), OPRND (h_gr_HI_index_of__DFLT_Rd));
+ current_cpu->h_gr_set (((UINT) 14), OPRND (psw));
+
+ return status;
+ #undef OPRND
+ #undef FLD
+ }
+
+
+ sem_status
+ xstormy16_write_sfmt_rrcgrimm4 (xstormy16_cpu* current_cpu, xstormy16_scache* sem, xstormy16_parexec* par_exec)
+ {
+ #define FLD(f) abuf->fields.sfmt_bngrimm4.f
+ #define OPRND(f) par_exec->operands.sfmt_rrcgrimm4.f
+ xstormy16_scache* abuf = sem;
+ unsigned long long written = abuf->written;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = 0; // dummy value for branches
+ sem_status status = SEM_STATUS_NORMAL; // ditto
+
+ current_cpu->h_gr_set (OPRND (h_gr_HI_index_of__DFLT_Rd_idx), OPRND (h_gr_HI_index_of__DFLT_Rd));
+ current_cpu->h_gr_set (((UINT) 14), OPRND (psw));
+
+ return status;
+ #undef OPRND
+ #undef FLD
+ }
+
+
+ sem_status
+ xstormy16_write_sfmt_shrgrimm (xstormy16_cpu* current_cpu, xstormy16_scache* sem, xstormy16_parexec* par_exec)
+ {
+ #define FLD(f) abuf->fields.sfmt_bngrimm4.f
+ #define OPRND(f) par_exec->operands.sfmt_shrgrimm.f
+ xstormy16_scache* abuf = sem;
+ unsigned long long written = abuf->written;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = 0; // dummy value for branches
+ sem_status status = SEM_STATUS_NORMAL; // ditto
+
+ current_cpu->h_gr_set (OPRND (h_gr_HI_index_of__DFLT_Rd_idx), OPRND (h_gr_HI_index_of__DFLT_Rd));
+ current_cpu->h_gr_set (((UINT) 14), OPRND (psw));
+
+ return status;
+ #undef OPRND
+ #undef FLD
+ }
+
+
+ sem_status
+ xstormy16_write_sfmt_asrgrgr (xstormy16_cpu* current_cpu, xstormy16_scache* sem, xstormy16_parexec* par_exec)
+ {
+ #define FLD(f) abuf->fields.sfmt_bccgrgr.f
+ #define OPRND(f) par_exec->operands.sfmt_asrgrgr.f
+ xstormy16_scache* abuf = sem;
+ unsigned long long written = abuf->written;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = 0; // dummy value for branches
+ sem_status status = SEM_STATUS_NORMAL; // ditto
+
+ current_cpu->h_gr_set (OPRND (h_gr_HI_index_of__DFLT_Rd_idx), OPRND (h_gr_HI_index_of__DFLT_Rd));
+ current_cpu->h_gr_set (((UINT) 14), OPRND (psw));
+
+ return status;
+ #undef OPRND
+ #undef FLD
+ }
+
+
+ sem_status
+ xstormy16_write_sfmt_asrgrimm (xstormy16_cpu* current_cpu, xstormy16_scache* sem, xstormy16_parexec* par_exec)
+ {
+ #define FLD(f) abuf->fields.sfmt_bngrimm4.f
+ #define OPRND(f) par_exec->operands.sfmt_asrgrimm.f
+ xstormy16_scache* abuf = sem;
+ unsigned long long written = abuf->written;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = 0; // dummy value for branches
+ sem_status status = SEM_STATUS_NORMAL; // ditto
+
+ current_cpu->h_gr_set (OPRND (h_gr_HI_index_of__DFLT_Rd_idx), OPRND (h_gr_HI_index_of__DFLT_Rd));
+ current_cpu->h_gr_set (((UINT) 14), OPRND (psw));
+
+ return status;
+ #undef OPRND
+ #undef FLD
+ }
+
+
+ sem_status
+ xstormy16_write_sfmt_set1lmemimm (xstormy16_cpu* current_cpu, xstormy16_scache* sem, xstormy16_parexec* par_exec)
+ {
+ #define FLD(f) abuf->fields.sfmt_set1lmemimm.f
+ #define OPRND(f) par_exec->operands.sfmt_set1lmemimm.f
+ xstormy16_scache* abuf = sem;
+ unsigned long long written = abuf->written;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = 0; // dummy value for branches
+ sem_status status = SEM_STATUS_NORMAL; // ditto
+
+ current_cpu->SETMEMQI (pc, OPRND (h_memory_QI_lmem8_idx), OPRND (h_memory_QI_lmem8));
+ current_cpu->h_gr_set (((UINT) 14), OPRND (psw));
+
+ return status;
+ #undef OPRND
+ #undef FLD
+ }
+
+
+ sem_status
+ xstormy16_write_sfmt_set1hmemimm (xstormy16_cpu* current_cpu, xstormy16_scache* sem, xstormy16_parexec* par_exec)
+ {
+ #define FLD(f) abuf->fields.sfmt_set1hmemimm.f
+ #define OPRND(f) par_exec->operands.sfmt_set1hmemimm.f
+ xstormy16_scache* abuf = sem;
+ unsigned long long written = abuf->written;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = 0; // dummy value for branches
+ sem_status status = SEM_STATUS_NORMAL; // ditto
+
+ current_cpu->SETMEMQI (pc, OPRND (h_memory_QI_hmem8_idx), OPRND (h_memory_QI_hmem8));
+ current_cpu->h_gr_set (((UINT) 14), OPRND (psw));
+
+ return status;
+ #undef OPRND
+ #undef FLD
+ }
+
+
+ sem_status
+ xstormy16_write_sfmt_bccgrgr (xstormy16_cpu* current_cpu, xstormy16_scache* sem, xstormy16_parexec* par_exec)
+ {
+ #define FLD(f) abuf->fields.sfmt_bccgrgr.f
+ #define OPRND(f) par_exec->operands.sfmt_bccgrgr.f
+ xstormy16_scache* abuf = sem;
+ unsigned long long written = abuf->written;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = 0; // dummy value for branches
+ sem_status status = SEM_STATUS_NORMAL; // ditto
+
+ if (written & (1ULL << 13))
+ {
+ current_cpu->branch (OPRND (pc), npc, status);
+ }
+ current_cpu->h_gr_set (((UINT) 14), OPRND (psw));
+
+ return status;
+ #undef OPRND
+ #undef FLD
+ }
+
+
+ sem_status
+ xstormy16_write_sfmt_bccgrimm8 (xstormy16_cpu* current_cpu, xstormy16_scache* sem, xstormy16_parexec* par_exec)
+ {
+ #define FLD(f) abuf->fields.sfmt_bccgrimm8.f
+ #define OPRND(f) par_exec->operands.sfmt_bccgrimm8.f
+ xstormy16_scache* abuf = sem;
+ unsigned long long written = abuf->written;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = 0; // dummy value for branches
+ sem_status status = SEM_STATUS_NORMAL; // ditto
+
+ if (written & (1ULL << 13))
+ {
+ current_cpu->branch (OPRND (pc), npc, status);
+ }
+ current_cpu->h_gr_set (((UINT) 14), OPRND (psw));
+
+ return status;
+ #undef OPRND
+ #undef FLD
+ }
+
+
+ sem_status
+ xstormy16_write_sfmt_bccimm16 (xstormy16_cpu* current_cpu, xstormy16_scache* sem, xstormy16_parexec* par_exec)
+ {
+ #define FLD(f) abuf->fields.sfmt_bccimm16.f
+ #define OPRND(f) par_exec->operands.sfmt_bccimm16.f
+ xstormy16_scache* abuf = sem;
+ unsigned long long written = abuf->written;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = 0; // dummy value for branches
+ sem_status status = SEM_STATUS_NORMAL; // ditto
+
+ if (written & (1ULL << 12))
+ {
+ current_cpu->branch (OPRND (pc), npc, status);
+ }
+ current_cpu->h_gr_set (((UINT) 14), OPRND (psw));
+
+ return status;
+ #undef OPRND
+ #undef FLD
+ }
+
+
+ sem_status
+ xstormy16_write_sfmt_bngrimm4 (xstormy16_cpu* current_cpu, xstormy16_scache* sem, xstormy16_parexec* par_exec)
+ {
+ #define FLD(f) abuf->fields.sfmt_bngrimm4.f
+ #define OPRND(f) par_exec->operands.sfmt_bngrimm4.f
+ xstormy16_scache* abuf = sem;
+ unsigned long long written = abuf->written;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = 0; // dummy value for branches
+ sem_status status = SEM_STATUS_NORMAL; // ditto
+
+ current_cpu->h_Rpsw_set (OPRND (Rpsw));
+ if (written & (1ULL << 5))
+ {
+ current_cpu->branch (OPRND (pc), npc, status);
+ }
+
+ return status;
+ #undef OPRND
+ #undef FLD
+ }
+
+
+ sem_status
+ xstormy16_write_sfmt_bngrgr (xstormy16_cpu* current_cpu, xstormy16_scache* sem, xstormy16_parexec* par_exec)
+ {
+ #define FLD(f) abuf->fields.sfmt_bccgrgr.f
+ #define OPRND(f) par_exec->operands.sfmt_bngrgr.f
+ xstormy16_scache* abuf = sem;
+ unsigned long long written = abuf->written;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = 0; // dummy value for branches
+ sem_status status = SEM_STATUS_NORMAL; // ditto
+
+ current_cpu->h_Rpsw_set (OPRND (Rpsw));
+ if (written & (1ULL << 5))
+ {
+ current_cpu->branch (OPRND (pc), npc, status);
+ }
+
+ return status;
+ #undef OPRND
+ #undef FLD
+ }
+
+
+ sem_status
+ xstormy16_write_sfmt_bnlmemimm (xstormy16_cpu* current_cpu, xstormy16_scache* sem, xstormy16_parexec* par_exec)
+ {
+ #define FLD(f) abuf->fields.sfmt_bnlmemimm.f
+ #define OPRND(f) par_exec->operands.sfmt_bnlmemimm.f
+ xstormy16_scache* abuf = sem;
+ unsigned long long written = abuf->written;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = 0; // dummy value for branches
+ sem_status status = SEM_STATUS_NORMAL; // ditto
+
+ if (written & (1ULL << 4))
+ {
+ current_cpu->branch (OPRND (pc), npc, status);
+ }
+
+ return status;
+ #undef OPRND
+ #undef FLD
+ }
+
+
+ sem_status
+ xstormy16_write_sfmt_bnhmemimm (xstormy16_cpu* current_cpu, xstormy16_scache* sem, xstormy16_parexec* par_exec)
+ {
+ #define FLD(f) abuf->fields.sfmt_bnhmemimm.f
+ #define OPRND(f) par_exec->operands.sfmt_bnhmemimm.f
+ xstormy16_scache* abuf = sem;
+ unsigned long long written = abuf->written;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = 0; // dummy value for branches
+ sem_status status = SEM_STATUS_NORMAL; // ditto
+
+ if (written & (1ULL << 4))
+ {
+ current_cpu->branch (OPRND (pc), npc, status);
+ }
+
+ return status;
+ #undef OPRND
+ #undef FLD
+ }
+
+
+ sem_status
+ xstormy16_write_sfmt_bcc (xstormy16_cpu* current_cpu, xstormy16_scache* sem, xstormy16_parexec* par_exec)
+ {
+ #define FLD(f) abuf->fields.sfmt_bcc.f
+ #define OPRND(f) par_exec->operands.sfmt_bcc.f
+ xstormy16_scache* abuf = sem;
+ unsigned long long written = abuf->written;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = 0; // dummy value for branches
+ sem_status status = SEM_STATUS_NORMAL; // ditto
+
+ if (written & (1ULL << 7))
+ {
+ current_cpu->branch (OPRND (pc), npc, status);
+ }
+
+ return status;
+ #undef OPRND
+ #undef FLD
+ }
+
+
+ sem_status
+ xstormy16_write_sfmt_bgr (xstormy16_cpu* current_cpu, xstormy16_scache* sem, xstormy16_parexec* par_exec)
+ {
+ #define FLD(f) abuf->fields.sfmt_jmp.f
+ #define OPRND(f) par_exec->operands.sfmt_bgr.f
+ xstormy16_scache* abuf = sem;
+ unsigned long long written = abuf->written;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = 0; // dummy value for branches
+ sem_status status = SEM_STATUS_NORMAL; // ditto
+
+ current_cpu->branch (OPRND (pc), npc, status);
+
+ return status;
+ #undef OPRND
+ #undef FLD
+ }
+
+
+ sem_status
+ xstormy16_write_sfmt_br (xstormy16_cpu* current_cpu, xstormy16_scache* sem, xstormy16_parexec* par_exec)
+ {
+ #define FLD(f) abuf->fields.sfmt_br.f
+ #define OPRND(f) par_exec->operands.sfmt_br.f
+ xstormy16_scache* abuf = sem;
+ unsigned long long written = abuf->written;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = 0; // dummy value for branches
+ sem_status status = SEM_STATUS_NORMAL; // ditto
+
+ current_cpu->branch (OPRND (pc), npc, status);
+
+ return status;
+ #undef OPRND
+ #undef FLD
+ }
+
+
+ sem_status
+ xstormy16_write_sfmt_jmp (xstormy16_cpu* current_cpu, xstormy16_scache* sem, xstormy16_parexec* par_exec)
+ {
+ #define FLD(f) abuf->fields.sfmt_jmp.f
+ #define OPRND(f) par_exec->operands.sfmt_jmp.f
+ xstormy16_scache* abuf = sem;
+ unsigned long long written = abuf->written;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = 0; // dummy value for branches
+ sem_status status = SEM_STATUS_NORMAL; // ditto
+
+ current_cpu->branch (OPRND (pc), npc, status);
+
+ return status;
+ #undef OPRND
+ #undef FLD
+ }
+
+
+ sem_status
+ xstormy16_write_sfmt_jmpf (xstormy16_cpu* current_cpu, xstormy16_scache* sem, xstormy16_parexec* par_exec)
+ {
+ #define FLD(f) abuf->fields.sfmt_jmpf.f
+ #define OPRND(f) par_exec->operands.sfmt_jmpf.f
+ xstormy16_scache* abuf = sem;
+ unsigned long long written = abuf->written;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = 0; // dummy value for branches
+ sem_status status = SEM_STATUS_NORMAL; // ditto
+
+ current_cpu->branch (OPRND (pc), npc, status);
+
+ return status;
+ #undef OPRND
+ #undef FLD
+ }
+
+
+ sem_status
+ xstormy16_write_sfmt_callrgr (xstormy16_cpu* current_cpu, xstormy16_scache* sem, xstormy16_parexec* par_exec)
+ {
+ #define FLD(f) abuf->fields.sfmt_jmp.f
+ #define OPRND(f) par_exec->operands.sfmt_callrgr.f
+ xstormy16_scache* abuf = sem;
+ unsigned long long written = abuf->written;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = 0; // dummy value for branches
+ sem_status status = SEM_STATUS_NORMAL; // ditto
+
+ current_cpu->SETMEMSI (pc, OPRND (h_memory_SI_sp_idx), OPRND (h_memory_SI_sp));
+ current_cpu->branch (OPRND (pc), npc, status);
+ current_cpu->h_gr_set (((UINT) 15), OPRND (sp));
+
+ return status;
+ #undef OPRND
+ #undef FLD
+ }
+
+
+ sem_status
+ xstormy16_write_sfmt_callrimm (xstormy16_cpu* current_cpu, xstormy16_scache* sem, xstormy16_parexec* par_exec)
+ {
+ #define FLD(f) abuf->fields.sfmt_br.f
+ #define OPRND(f) par_exec->operands.sfmt_callrimm.f
+ xstormy16_scache* abuf = sem;
+ unsigned long long written = abuf->written;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = 0; // dummy value for branches
+ sem_status status = SEM_STATUS_NORMAL; // ditto
+
+ current_cpu->SETMEMSI (pc, OPRND (h_memory_SI_sp_idx), OPRND (h_memory_SI_sp));
+ current_cpu->branch (OPRND (pc), npc, status);
+ current_cpu->h_gr_set (((UINT) 15), OPRND (sp));
+
+ return status;
+ #undef OPRND
+ #undef FLD
+ }
+
+
+ sem_status
+ xstormy16_write_sfmt_callgr (xstormy16_cpu* current_cpu, xstormy16_scache* sem, xstormy16_parexec* par_exec)
+ {
+ #define FLD(f) abuf->fields.sfmt_jmp.f
+ #define OPRND(f) par_exec->operands.sfmt_callgr.f
+ xstormy16_scache* abuf = sem;
+ unsigned long long written = abuf->written;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = 0; // dummy value for branches
+ sem_status status = SEM_STATUS_NORMAL; // ditto
+
+ current_cpu->SETMEMSI (pc, OPRND (h_memory_SI_sp_idx), OPRND (h_memory_SI_sp));
+ current_cpu->branch (OPRND (pc), npc, status);
+ current_cpu->h_gr_set (((UINT) 15), OPRND (sp));
+
+ return status;
+ #undef OPRND
+ #undef FLD
+ }
+
+
+ sem_status
+ xstormy16_write_sfmt_callfimm (xstormy16_cpu* current_cpu, xstormy16_scache* sem, xstormy16_parexec* par_exec)
+ {
+ #define FLD(f) abuf->fields.sfmt_jmpf.f
+ #define OPRND(f) par_exec->operands.sfmt_callfimm.f
+ xstormy16_scache* abuf = sem;
+ unsigned long long written = abuf->written;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = 0; // dummy value for branches
+ sem_status status = SEM_STATUS_NORMAL; // ditto
+
+ current_cpu->SETMEMSI (pc, OPRND (h_memory_SI_sp_idx), OPRND (h_memory_SI_sp));
+ current_cpu->branch (OPRND (pc), npc, status);
+ current_cpu->h_gr_set (((UINT) 15), OPRND (sp));
+
+ return status;
+ #undef OPRND
+ #undef FLD
+ }
+
+
+ sem_status
+ xstormy16_write_sfmt_icallrgr (xstormy16_cpu* current_cpu, xstormy16_scache* sem, xstormy16_parexec* par_exec)
+ {
+ #define FLD(f) abuf->fields.sfmt_jmp.f
+ #define OPRND(f) par_exec->operands.sfmt_icallrgr.f
+ xstormy16_scache* abuf = sem;
+ unsigned long long written = abuf->written;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = 0; // dummy value for branches
+ sem_status status = SEM_STATUS_NORMAL; // ditto
+
+ current_cpu->SETMEMHI (pc, OPRND (h_memory_HI_add__DFLT_sp_4_idx), OPRND (h_memory_HI_add__DFLT_sp_4));
+ current_cpu->SETMEMSI (pc, OPRND (h_memory_SI_sp_idx), OPRND (h_memory_SI_sp));
+ current_cpu->branch (OPRND (pc), npc, status);
+ current_cpu->h_gr_set (((UINT) 15), OPRND (sp));
+
+ return status;
+ #undef OPRND
+ #undef FLD
+ }
+
+
+ sem_status
+ xstormy16_write_sfmt_icallgr (xstormy16_cpu* current_cpu, xstormy16_scache* sem, xstormy16_parexec* par_exec)
+ {
+ #define FLD(f) abuf->fields.sfmt_jmp.f
+ #define OPRND(f) par_exec->operands.sfmt_icallgr.f
+ xstormy16_scache* abuf = sem;
+ unsigned long long written = abuf->written;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = 0; // dummy value for branches
+ sem_status status = SEM_STATUS_NORMAL; // ditto
+
+ current_cpu->SETMEMHI (pc, OPRND (h_memory_HI_add__DFLT_sp_4_idx), OPRND (h_memory_HI_add__DFLT_sp_4));
+ current_cpu->SETMEMSI (pc, OPRND (h_memory_SI_sp_idx), OPRND (h_memory_SI_sp));
+ current_cpu->branch (OPRND (pc), npc, status);
+ current_cpu->h_gr_set (((UINT) 15), OPRND (sp));
+
+ return status;
+ #undef OPRND
+ #undef FLD
+ }
+
+
+ sem_status
+ xstormy16_write_sfmt_icallfimm (xstormy16_cpu* current_cpu, xstormy16_scache* sem, xstormy16_parexec* par_exec)
+ {
+ #define FLD(f) abuf->fields.sfmt_jmpf.f
+ #define OPRND(f) par_exec->operands.sfmt_icallfimm.f
+ xstormy16_scache* abuf = sem;
+ unsigned long long written = abuf->written;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = 0; // dummy value for branches
+ sem_status status = SEM_STATUS_NORMAL; // ditto
+
+ current_cpu->SETMEMHI (pc, OPRND (h_memory_HI_add__DFLT_sp_4_idx), OPRND (h_memory_HI_add__DFLT_sp_4));
+ current_cpu->SETMEMSI (pc, OPRND (h_memory_SI_sp_idx), OPRND (h_memory_SI_sp));
+ current_cpu->branch (OPRND (pc), npc, status);
+ current_cpu->h_gr_set (((UINT) 15), OPRND (sp));
+
+ return status;
+ #undef OPRND
+ #undef FLD
+ }
+
+
+ sem_status
+ xstormy16_write_sfmt_iret (xstormy16_cpu* current_cpu, xstormy16_scache* sem, xstormy16_parexec* par_exec)
+ {
+ #define FLD(f) abuf->fields.fmt_empty.f
+ #define OPRND(f) par_exec->operands.sfmt_iret.f
+ xstormy16_scache* abuf = sem;
+ unsigned long long written = abuf->written;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = 0; // dummy value for branches
+ sem_status status = SEM_STATUS_NORMAL; // ditto
+
+ current_cpu->branch (OPRND (pc), npc, status);
+ current_cpu->h_gr_set (((UINT) 14), OPRND (psw));
+ current_cpu->h_gr_set (((UINT) 15), OPRND (sp));
+
+ return status;
+ #undef OPRND
+ #undef FLD
+ }
+
+
+ sem_status
+ xstormy16_write_sfmt_ret (xstormy16_cpu* current_cpu, xstormy16_scache* sem, xstormy16_parexec* par_exec)
+ {
+ #define FLD(f) abuf->fields.fmt_empty.f
+ #define OPRND(f) par_exec->operands.sfmt_ret.f
+ xstormy16_scache* abuf = sem;
+ unsigned long long written = abuf->written;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = 0; // dummy value for branches
+ sem_status status = SEM_STATUS_NORMAL; // ditto
+
+ current_cpu->branch (OPRND (pc), npc, status);
+ current_cpu->h_gr_set (((UINT) 15), OPRND (sp));
+
+ return status;
+ #undef OPRND
+ #undef FLD
+ }
+
+
+ sem_status
+ xstormy16_write_sfmt_mul (xstormy16_cpu* current_cpu, xstormy16_scache* sem, xstormy16_parexec* par_exec)
+ {
+ #define FLD(f) abuf->fields.fmt_empty.f
+ #define OPRND(f) par_exec->operands.sfmt_mul.f
+ xstormy16_scache* abuf = sem;
+ unsigned long long written = abuf->written;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = 0; // dummy value for branches
+ sem_status status = SEM_STATUS_NORMAL; // ditto
+
+ current_cpu->h_gr_set (((UINT) 0), OPRND (R0));
+ current_cpu->h_gr_set (((UINT) 1), OPRND (R1));
+ current_cpu->h_gr_set (((UINT) 14), OPRND (psw));
+
+ return status;
+ #undef OPRND
+ #undef FLD
+ }
+
+
+ sem_status
+ xstormy16_write_sfmt_nop (xstormy16_cpu* current_cpu, xstormy16_scache* sem, xstormy16_parexec* par_exec)
+ {
+ #define FLD(f) abuf->fields.fmt_empty.f
+ #define OPRND(f) par_exec->operands.sfmt_nop.f
+ xstormy16_scache* abuf = sem;
+ unsigned long long written = abuf->written;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = 0; // dummy value for branches
+ sem_status status = SEM_STATUS_NORMAL; // ditto
+
+
+ return status;
+ #undef OPRND
+ #undef FLD
+ }
+ =======
using namespace xstormy16;
*************** xstormy16_write_sfmt_nop (xstormy16_cpu*
*** 1863,1866 ****
--- 3675,3679 ----
#undef OPRND
#undef FLD
}
+ >>>>>>> 1.2
Index: sid/include/sidcpuutil.h
===================================================================
RCS file: /cvs/src/src/sid/include/sidcpuutil.h,v
retrieving revision 1.23
diff -c -p -r1.23 sidcpuutil.h
*** sid/include/sidcpuutil.h 29 Nov 2002 05:52:42 -0000 1.23
--- sid/include/sidcpuutil.h 15 Jan 2003 19:55:17 -0000
***************
*** 1,6 ****
// sidcpuutil.h - Elements common to CPU models. -*- C++ -*-
! // Copyright (C) 1999, 2000, 2001, 2002 Red Hat.
// This file is part of SID and is licensed under the GPL.
// See the file COPYING.SID for conditions for redistribution.
--- 1,6 ----
// sidcpuutil.h - Elements common to CPU models. -*- C++ -*-
! // Copyright (C) 1999, 2000, 2001, 2002, 2003 Red Hat.
// This file is part of SID and is licensed under the GPL.
// See the file COPYING.SID for conditions for redistribution.
*************** namespace sidutil
*** 283,289 ****
virtual void print_insn_summary (sid::host_int_4)
{
std::cerr << "instruction count: " << this->total_insn_count << " "
! << "simulated cycles: " << this->total_latency << std::endl;
}
virtual void stepped (sid::host_int_4 n)
{
--- 283,289 ----
virtual void print_insn_summary (sid::host_int_4)
{
std::cerr << "instruction count: " << this->total_insn_count << " "
! << "simulated cycles: " << this->total_latency + this->total_insn_count << std::endl;
}
virtual void stepped (sid::host_int_4 n)
{