Re: tabling constant-field-beyond-base patch

[Doug Evans <dje at sebabeach dot org>]

   Date: Thu, 13 May 2004 20:23:17 +0100
   From: "Adrian Ashley" <adrian.ashley@broadcom.com>

   Way back in Aug-2003, Doug Evans wrote:
   > Finishing up the remaining bits of this patch are proving difficult. 
   > [N.B. The issues aren't of a technical nature.] So I'm tabling the
   > current state of the patch here.
   > 
   > I hope to have the difficulties resolved RSN.  Sigh.

Update: The issues still aren't resolved and the ball isn't in my court
to resolve them.  Sigh.

   I'm working on a port to a (little-endian) machine which has some 64-bit
   instructions which are extended versions of 32-bit ones - i.e. ambiguous
   in the lower 32-bits but distinguishable by looking at some of the upper
   32-bits.  CGEN currently goes bong in -build-decode-table-entry when it
   detects the ambiguity.

   In my search through the archives it looks like this work might be a
   good starting point.  Other postings referred to the possibility of
   making CGEN_INSN_INT a long long and removing all the assumptions that
   it is actually 32 bits - though replacing them with only slightly less
   rigid assumptions that it's "32 or 64".

   Has this problem been solved already?  If not, can the sages offer
   advice as to the most fruitful way to proceed?  I'm currently trying the
   "CGEN_INSN_INT is long long" approach, in the absence of fully 
   understanding the bigger picture.

IMO, without actually sitting down and studying the ISA in question,
extending CGEN_INSN_INT isn't the way to go.  CGEN_INSN_INT is a
special case of the general solution, created to simplify handling of
several popular architectures (32-bit riscs).
Trying to generalize it has and will lead to issues, further complicating
things.

Have you looked at not using CGEN_INSN_INT and treating instructions as
just a set of bytes (i.e. "cisc-like") ?