Re: delayed branches and zero overhead loops

["Frank Ch. Eigler" <fche at redhat dot com>]

Hi -

> The problem is that long immediates are available to a lot of different
> instruction formats by using an encoding that looks like 'core register 62'.
> Most of the instructions have two fields that can specify that.
> Trying to express this with separate formats is not feasible, a this would
> only quadruple the number of insn definition (double the number of formats
> but awkward decoding), 

This part does not look that scary.  It's milder than m68k addressing
modes.  You can use cgen macros to generate instruction variants like
that.  We have processed ports with hundreds or maybe even thousands
of instructions, and while it ain't fast to run through, it still
works.

> but also cause trouble making the decoder generator comprehend where
> the boundaries between the different formats are.

The decoder generator is fully automatic.  If you represent decodable
bits without cheating, it will do a reasonable job.

- FChE