[Fwd: Hitachi SH-2 UBC help needed]

[William Gatliff <gatliff AT haulpak dot com>]

--
William A. Gatliff
Senior Design Engineer
Komatsu Mining Systems
To teach is to learn.

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• Subject: Hitachi SH-2 UBC help needed
• From: bgat AT usa dot net
• Date: Thu, 16 Sep 1999 17:13:31 GMT
• Newsgroups: comp.arch.embedded
• Organization: Deja.com - Share what you know. Learn what you don't.
• Xref: newsfeed.slurp.net comp.arch.embedded:70731

Greetings, kind souls...

Has anyone used the Hitachi SH-2 microprocessor's User Break Controller
(UBC)?  This peripheral is available on (at least) the 7040 series, and
I'm considering using it as a way to generate an exception after each
instruction execution, to simplify my "stepi" implementation in a GNU
debugger stub.

All the examples in the SH-2 manual show the case where you know the
address of an instruction a-priori, and you then set that address in the
UBAR registers.  If I stick with this approach, then I'm forced to do a
bit of disassembly at runtime to determine where the instruction about
to be executed will go, so that I can generate a UBC exception after it
finishes.

What I would prefer to do is simply disable interrupts, configure the
UBC to generate an exception on *any* fetch (UBAMRH/L == 0xffff), and
then do an RTE.  What I'm hoping is that the instruction waiting after
the RTE will finish before the UBC exception is taken...

Is this feasible?  The japlish documentation isn't really clear on this
point, but it would seem to be a real oversight on Hitachi's part if
this wouldn't work...

Thanks!

b.g.


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