RE: gcc asm constraint for registers on ppc

["Scott Howard" <scotth at estc dot com>]

Try using the "b" constraint instead. It tells gcc to use a 'base' register,
which is any register that may be used as a base address in a memory
reference (ie any register except r0).

-----Original Message-----
From: crossgcc-owner@sourceware.cygnus.com
[mailto:crossgcc-owner@sourceware.cygnus.com]On Behalf Of Daniel Kahlin
Sent: Tuesday, December 14, 1999 2:51 AM
To: crossgcc@sourceware.cygnus.com
Cc: tlr@netinsight.net; johryd@netinsight.net
Subject: Q: gcc asm constraint for registers on ppc



I have written a routine which makes atomic 64-bit memory accesses.
This is what the crucial part looks like:

/* _data_ is a pointer to 64-bits of data.
   _addr_ is a 64-bit aligned address.    */

    asm volatile

	"mr     3,%1;"
        "lfd    0,0(3);"
	"mr     3,%0;"
        "stfd   0,0(3);"
        "eieio;"
        : /* no output */
        : /* %0 */ "r" (_addr_),
          /* %1 */ "r" (_data_)
        : "r3", "fr0", "memory"
        );

Ok, now this works but I want to write it like this:

    asm volatile

        "lfd    0,0(%1);"
        "stfd   0,0(%0);"
        "eieio;"
        : /* no output */
        : /* %0 */ "r" (_addr_),
          /* %1 */ "r" (_data_)
        : "fr0", "memory"
        );

The problem here is that with the "r" constraint, gcc chooses "r0" sometimes
which does not produce valid powerpc assembly code in this case.

What asm constraint will make gcc use _any_ general purpose register except
"r0" (on powerpc)?

/Daniel

--
Daniel Kahlin                    <daniel.kahlin@netinsight.net>
Hardware System Designer         phone:  +46-8-685 04 00
Net Insight AB                   direct: +46-8-685 04 08
URL: http://www.netinsight.net   fax:    +46-8-685 04 20

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