Re: optimizing gcc output for ARM

[Richard Earnshaw <rearnsha at arm dot com>]

> If I compile the following lines
> 
>   for (i=0;i<10;i++) {
>     asm volatile ("mla %0,%3,%2,%1":"=r" (sum):"r" (coeff), "r" (sample), "r" (sum));
>   }

Why not just write this as ordinary C?  Gcc can then hoist the multiply 
right out of the loop, since it is invariant:

int bar(int coeff, int sample)
{
  int sum = 0;
  int i;

  for (i=0;i<10;i++) {
    sum += coeff * sample;
  }
  return sum;
}

gives me (gcc -O2):

bar:
        mul     r1, r0, r1
        mov     r3, #9
.L13:
        subs    r3, r3, #1
        bpl     .L13
        add     r0, r1, r1, asl #2
        mov     r0, r0, asl #1
        mov     pc, lr

> I get the assembler output
> .L3:
> 	ldr	r3, [fp, #-28]
> 	cmp	r3, #9
> 	ble	.L6
> 	b	.L4
> .L6:
> 	ldr	r3, [fp, #-16]
> 	ldr	r2, [fp, #-20]
> 	ldr	r1, [fp, #-24]
> 	ldr	ip, [fp, #-16]
> 	mla r3,r1,r2,r3
> 	mov	r2, r3
> 	str	r2, [fp, #-16]
> .L5:
> 	ldr	r3, [fp, #-28]
> 	add	r2, r3, #1
> 	str	r2, [fp, #-28]
> 	b	.L3
> 
> (explanation: [fp, #-16]: sum; [fp, #-20]:coeff;  [fp, #-24]:sample)

Are you turning the optimizer on?  I get:

        mov     r3, r0
        mov     r2, #9
        mov     r0, #0
.L6:
        mla r0,r0,r1,r3
        subs    r2, r2, #1
        bpl     .L6
        mov     pc, lr


> 
> I can life with the fact that gcc doesn´t recognize the 
> special MAC instruction from the ARM, but the line
> after it is stupid,
> 	str	r3, [fp, #-16]
> would work fine too, and is one ins. shorter. 
> And the line above it is not nessesary, too.
> 1.) Why does the gcc produce such output?
> 2.) How can I avoid this?
> 

GCC does know how to generate a multiply-accumulate instruction, and will 
use it when necessary (provided the optimizer is enabled).  But your code 
in this case is displaying all the signs of not being optimized at all.


Richard.


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