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Hello, I'm now porting gcc to the embeded processor, which in short has 1 accumulator register and 3 index registers (BASE_REGS in gcc sence). Instruction set of this processor is poor enough. ;-)) Most of the arithmetic operations deals with accumulator register and memory operand which can be addressed with index regs only. One of this index regs I'm using as stack pointer, so the only 2 remaining index regs can be used for gcc needs. The port is mostly complete, but I'm encountering some problems now. The first one is the "Unable to find a register to spill" problem. This occures when gcc tries to occupy too many index registers in most cases. The simplest example for this problems is the following function: void rstrcpy(int * src, int * dst) { while (*dst++ = *src++); } When my gcc port compiles this code with just "xgcc test3.c -S" I've no luck. I've got "Unable to find a register to spill". But when I simply add -fomit-frame-pointer everything is OK, and the resulting asm file looks fine (r1 is the stack pointer, r2, r3 is the index registers and the rr is the accumulator register): mov r1:2,rr mov rr,r3 mov r1:3,rr mov rr,r2 L5: mov r3:0,rr mov rr,r2:0 inci r3,1 inci r2,1 ; tstqi bnea 0,L5 So, as seems "Unable to find a register to spill" occures when gcc did not find index registers enough for this sequence. So, when I've used "-fomit-frame-pointer" r2 (my frame pointer) was freed and gcc compiles successfully. But why gcc tries to place both pointers on to the regs? Unfortunatly my gcc port can't handle at all the following function: void rstrcpy(int * src, int * dst, int * dst2) { while (*dst2++ = *dst++ = *src++); } Theoreticaly gcc should pro duc e something like this: mov r1:2,rr mov rr,r3 L5: mov r1:3,rr mov rr,r2 mov r3:0,rr mov rr,r2:0 inci r2,1 mov r2,rr mov rr,r1:3 mov r1:4,rr mov rr,r2 mov r3:0,rr mov rr,r2:0 inci r2,1 mov r2,rr mov rr,r1:4 inci r3,1 ; tstqi bnea 0,L5 So, what to do? I'm already make the following defines #define SMALL_REGISTER_CLASSES 1 #define CLASS_LIKELY_SPILLED_P(CLASS) 1 but has no luck in the spills. Any one can help me with this problem? And the second problem is the absence of the "compare" instructions in this processor. So I've defined this operation with substraction instructions, but as side effect my compare instruction alters the accumulator register, so I've tried to write something like: (define_insn "cmpqi" [(set (cc0) (compare (match_operand:QI 0 "register_operand" "r") (match_operand:QI 1 "general_operand" "m"))) (clobber (reg:QI 0))] but again has no luck. :-(( Because gcc "performs" this insn in parallel and the only valid operand also comes in reg:QI 0, gcc aborts. So, can anyone advise me how to specify clobbering correctly? Thanks, Oleg. ------ Want more information? See the CrossGCC FAQ, http://www.objsw.com/CrossGCC/ Want to unsubscribe? Send a note to crossgcc-unsubscribe@sourceware.cygnus.com
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