Re: Interesting thing

["RAY Electronic-Design GmbH" <info at raygmbh dot de>]

As i also want to use GCC for arm target, i was interested about this and
tried it with

gcc version 2.95.3-4 (cygwin special)

arm-elf-gcc.exe -g -O2 -c volatile_test.c
arm-elf-objdump.exe -s -d volatile_test.o


00000000 <broken>:
   0: e1a0c00d  mov ip, sp
   4: e92dd800  stmdb sp!, {fp, ip, lr, pc}
   8: e24cb004  sub fp, ip, #4 ; 0x4
   c: e3e01c7d  mvn r1, #32000 ; 0x7d00
  10: e24110bf  sub r1, r1, #191 ; 0xbf
  14: e3e00c7d  mvn r0, #32000 ; 0x7d00     *** addresses set-up
  18: e5d13000  ldrb r3, [r1] ;             *** read TSYN
  1c: e24000be  sub r0, r0, #190 ; 0xbe     *** address-calculation for TSTR
  20: e20330fe  and r3, r3, #254 ; 0xfe     *** and operation
  24: e5c13000  strb r3, [r1] ;             *** write TSYN
  28: e3a02000  mov r2, #0 ; 0x0
  2c: e5c02000  strb r2, [r0]               *** write 0 from r2 to TSTR
  30: e91ba800  ldmdb fp, {fp, sp, pc}

00000034 <x>:
  34: e1a0c00d  mov ip, sp
  38: e92dd800  stmdb sp!, {fp, ip, lr, pc}
  3c: e3e02c7d  mvn r2, #32000 ; 0x7d00
  40: e55230bf  ldrb r3, [r2, -#191]
  44: e24cb004  sub fp, ip, #4 ; 0x4
  48: e20330fe  and r3, r3, #254 ; 0xfe
  4c: e54230bf  strb r3, [r2, -#191]
  50: e91ba800  ldmdb fp, {fp, sp, pc}

00000054 <y>:
  54: e1a0c00d  mov ip, sp
  58: e92dd800  stmdb sp!, {fp, ip, lr, pc}
  5c: e24cb004  sub fp, ip, #4 ; 0x4
  60: e3e02c7d  mvn r2, #32000 ; 0x7d00
  64: e3a03000  mov r3, #0 ; 0x0
  68: e54230be  strb r3, [r2, -#190]
  6c: e91ba800  ldmdb fp, {fp, sp, pc}

This works as i am used to it and expected it. So your problem seems to be
target specific.

Raymund Hofmann

----- Original Message -----
From: "Tony Bryant" <brd@paradise.net.nz>
To: "CrossGCC (E-mail)" <crossgcc@sourceware.cygnus.com>
Sent: Saturday, June 16, 2001 9:44 AM
Subject: Interesting thing


> Try compiling the following c++ program:
>
> // start here
>
> #define TSTR  (*(volatile unsigned char *)(0xFFFF8240))
> #define TSYN  (*(volatile unsigned char *)(0xFFFF8241))
>
> inline void x()
> {
> TSTR=TSTR & 0xFE;
> }
>
> inline void y()
> {
> TSYN=0;
> }
>
> void broken()
> {
> x();
> y();
> }
>
> // stop here
>
> save this as "t.cc"
>
> now run:
> gcc -g -O2 -c t.cc
> objdump -s -d t.o
>
> and you get:
>
> Disassembly of section .text:
>
> 00000000 <broken__Fv>:
>    0: 55                   push   %ebp
>    1: a0 40 82 ff ff       mov    0xffff8240,%al
>    6: 25 fe 00 00 00       and    $0xfe,%eax
>    b: a2 40 82 ff ff       mov    %al,0xffff8240
>   10: a0 40 82 ff ff       mov    0xffff8240,%al
>   15: c6 05 41 82 ff ff 00  movb   $0x0,0xffff8241
>   1c: 89 e5                mov    %esp,%ebp
>   1e: a0 41 82 ff ff       mov    0xffff8241,%al
>   23: 5d                   pop    %ebp
>   24: c3                   ret
>
> Why are the instructions at 0x10 & 0x1e included?
> Is there any way around this apart from dropping the volatile?
> Have I misinterpreted the meaning of volatile?
>
> BTW This does a similar thing on the sh target as well:
>
> Disassembly of section .text:
>
> 00000000 <_broken__Fv>:
>    0: 2f e6       mov.l r14,@-r15
>    2: 91 0b       mov.w 1c <_broken__Fv+0x1c>,r1 ! 0x8240
>    4: 6e f3       mov r15,r14
>    6: 60 10       mov.b @r1,r0
>    8: c9 fe       and #-2,r0
>    a: 21 00       mov.b r0,@r1
>    c: 61 10       mov.b @r1,r1
>    e: 92 06       mov.w 1e <_broken__Fv+0x1e>,r2 ! 0x8241
>   10: e1 00       mov #0,r1
>   12: 22 10       mov.b r1,@r2
>   14: 61 20       mov.b @r2,r1
>   16: 6f e3       mov r14,r15
>   18: 00 0b       rts
>   1a: 6e f6       mov.l @r15+,r14
>   1c: 82 40       .word 0x8240
>   1e: 82 41       .word 0x8241
>
> Interesting enough, it works fine if the file is a C program (i.e. you've
> called it t.c or similar.
>
>
> ------
> Want more information?  See the CrossGCC FAQ,
http://www.objsw.com/CrossGCC/
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crossgcc-unsubscribe@sourceware.cygnus.com
>


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