Re: Coldfire/M68K 32 bit RAM access?

[Peter Barada <pbarada at mail dot wm dot sps dot mot dot com>]

>I'm working on a custom embedded Coldfire processor board that has
>512K of SRAM on it.
>This SRAM only allows 32 bit reads and writes, and the lower two address 
>bits do not connect to the coldfire.
>There is nothing on the board to try to compensate for this either. I had 
>worked with other boards that had an EDAC that would do a read-modify-write 
>operation for 8 or 16 bit operations.
>
>Am I correct in thinking that GCC compiled code will not run on this?
>
>I see immediate problems when I move the stack from internal ( on chip ) 
>SRAM to this on-board SRAM.

Is it possible to cache that area of memory?  If so then the caches
will make 32 bit accesses to load/store cache lines....

-- 
Peter Barada                             Peter.Barada@motorola.com
Wizard                                   781-852-2768 (direct)
WaveMark Solutions(A Motorola Company)   781-270-0193 (fax)

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