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Haa die Pieter, On Mon, Mar 21, 2005 at 10:17:58AM -0800, Pieter Arnout wrote: > (1) I want to define a ROM and RAM memory region with part of the RAM > memory region as cacheable and the other part as having an uncacheable > path to the CPU. This isn't done in the linker script. Whether a memory region is accessed as cacheable or not is typically determined by page table attributes. You might want to read "Computer architecture: a quantitative approach" by Hennessy and Patterson, in which this is all very clearly explained. --L ------ Want more information? See the CrossGCC FAQ, http://www.objsw.com/CrossGCC/ Want to unsubscribe? Send a note to crossgcc-unsubscribe@sources.redhat.com
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