Re: ldrb vs ldrh in gcc-3.4.4 (ARM)

[Bill Gatliff <bgat at billgatliff dot com>]

Richard Earnshaw wrote:

> On Wed, 2005-08-17 at 15:43, Steven Scholz wrote:
>  
>
> > Richard,
> >
> >    
> >
> > > > > First google hit on "AT91RM9200":
> > > > > 	http://www.atmel.com/dyn/products/product_card.asp?part_id=2983
> > > > >
> > > > > That page mentions that it's an ARM920T core.  First google hit on
> > > > > "ARM920T":
> > > > > 	http://www.arm.com/products/CPUs/ARM920T.html
> > > > >
> > > > > That page mentions 'ARMv4T'.
> > > > >          
> > > > Thanks for googling for me! ;-)
> > > >
> > > > So I use either -march=armv4 _OR_ -mcpu=arm920t. Right?
> > > >
> > > > (Using both brought me a warning about conflicting).
> > > >        
> > > the arm920t is an armv4t device (the 't' is thumb).
> > >
> > > Basically, there are two options, -march=xxx and -mtune=xxx that are
> > > independent (one selects the available instructions, the other the best
> > > way to use that set for the intended cpu).  -mcpu=xxx is shorthand that
> > > can be used to set both options in one go: so -mcpu=xxx is equivalent to
> > > writing -march=<arch_of(xxx)> -mtune=xxx.
> > >
> > > Note that to get Thumb code you have to use -mthumb; it's not sufficient
> > > to tell the compiler that you have thumb instructions available.
> > >      
> > Thanks a million. Maybe you could explain the difference of arm920t and arm9tdmi 
> > as well, please?
> >    
>
> The arm9tdmi is the main 'core' of the CPU.  The arm920t is the core
> plus the associated cache, mmu, and system registers.   Different models
> all have substantially the same 'core' but may have different (or
> missing) additional parts.  Thus arm920t arm926t arm966t etc.
>
> It's not quite as simple as that (for marketing reasons), but that's the
> one paragraph summary.
>
> See the ARM web site for more details of the different products
> (www.arm.com).
>  

Just to supplement Richard's excellent answer...


According to the "ARM Architecture Reference Manual", David Seal, 2000:

"T" variants: Thumb instruction set support.
"M" variants: Long multiply instruction support (32x32->64 and 32x32+64->64)
"E" variants: DSP-related instruction support.

So, an "ARMv5TE" is an ARMv5 instruction set core, with Thumb and 
DSP-related instruction support added.  Interestingly, "ARMv5TExP" is 
all that EXCEPT a "P", which is certain DSP architectures that omitted 
ldrd, strd, mcrr, mcrc and pld instructions.

So, that's ARM core descriptions.  As for products, which have names 
like "arm7tdmi", that's a term that traces to an ARM core name as 
described above (and documented in the chip's literature, usually with a 
much lower number like "armv4"), plus some extra features.  Like:

"D" on-chip debugging unit.
"I" EmbeddedICE hardware suport.

...  according to "ARM System On Chip Architecture", Steve Furber, 2000.

And I bet if you hunt around long enough, you find that the "7" in that 
leads somewhere telling you where the cache is connected vs. the MMU, or 
something like that...

XScale and StrongARM are the odd ones, as they're not *quite* completely 
and entirely ARM chips like the rest of ARM chips are...  Thank Intel 
and DEC for that.  :)

Clear enough?

(I'm getting ready to teach a course on this for UCSD, the history of 
ARM and it's various ways of identifying chips is, well, interesting...)


b.g.

--
Bill Gatliff
bgat@billgatliff.com


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