This is the mail archive of the crossgcc@sourceware.org mailing list for the crossgcc project.

See the CrossGCC FAQ for lots more information.


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]
Other format: [Raw text]

Re: ldrb vs ldrh in gcc-3.4.4 (ARM)


Richard Earnshaw wrote:

The arm9tdmi is the main 'core' of the CPU.  The arm920t is the core
plus the associated cache, mmu, and system registers.   Different models
all have substantially the same 'core' but may have different (or
missing) additional parts...


Thanks. So when I am using Freescale i.MX and Atmel AT91RM9200 which are both arm920t I rather use

   GCC_EXTRA_CONFIG="--with-float=soft --with-cpu=arm920t \
                         --enable-cxx-flags=-mcpu=arm920t"

instead of

   GCC_EXTRA_CONFIG="--with-float=soft --with-cpu=arm9tdmi \
                         --enable-cxx-flags=-mcpu=arm9tdmi"

when building the toolchain. Right?

ARGH! There's no "--with-cpu=arm920t" !



This has been fixed in gcc-4.0 and it's also been fixed in the CodeSourcery version of 3.4 (http://www.codesourcery.com/gnu_toolchains/arm/).


gcc/config/arm/arm.h only knows

#define TARGET_CPU_arm9         0x0080
#define TARGET_CPU_arm9tdmi     0x0080

I suppose it's defined as 0x0080 as well!?


So when arm9tdmi is only thre core without caches will "--with-cpu=arm9tdmi" use the caches in a sane way ?

It probably makes no difference in 3.4 and earlier. It might have a small effect in later versions, but gcc doesn't really understand caches and their layout yet.
Ok.

Thanks.

--
Steven

------
Want more information?  See the CrossGCC FAQ, http://www.objsw.com/CrossGCC/
Want to unsubscribe? Send a note to crossgcc-unsubscribe@sources.redhat.com


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]