Problem compiling Icarus Verilog w/ latest binutils

[Stephen Williams <steve at icarus dot com>]

(P.S. I'm not subscribed, so please CC me on this thread.)

I'm having trouble with Icarus Verilog and the latest version of binutils
for Cygwin. I'm getting reports like this:

====================================================
.. ...
cd vpi ; make all
make[1]: Entering directory `/tmp/verilog-20001119/vpi'
gcc -shared -o system.vpi sys_table.o sys_display.o sys_finish.o sys_random.o sys_readmem.o sys_readmem_lex.o sys_time.o sys_vcd.o -Wl,--enable-auto-image-base -L../vvm -lvvm -lvpip
Cannot export _bss_end__: symbol not defined
Cannot export _bss_start__: symbol not defined
Cannot export _data_end__: symbol not defined
Cannot export _data_start__: symbol not defined
collect2: ld returned 1 exit status
make[1]: *** [system.vpi] Error 1
make[1]: Leaving directory `/tmp/verilog-20001119/vpi'
make: *** [all] Error 2
====================================================

I have confirmed that this problem occurs with binutils-20001025, but
does not happen with the -200006xx version of binutils. A lot of tricky
stuff is happening with the compile of Icarus Verilog, because it uses
dlopen to load the system.vpi module.

I admit to being a bit overwhelmed by the Cygwin compile process, but
perhaps Venkat can shed some light on this problem as well.
-- 
Steve Williams                "The woods are lovely, dark and deep.
steve@icarus.com              But I have promises to keep,
steve@picturel.com            and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."



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