Making Make build multiple targets in a single compiler invocation

[Jonathan Kamens <jik at curl dot com>]

I seem to recall that someone mentioned on this list recently that one
way to speed up Make is to make it specify multiple source files in a
single compiler invocation, rather than using a separate compiler
invocation for every file being compiled, to reduce the number of
spawns.

Now, when I want to try to implement something like that within our
build infrastructure, I can't find the message in which the idea was
mentioned, despite spending quite a while searching through the list
archives.  I just must not be using the right keywords :-(.

I've also spent some time reading through the Make documentation and
trying to come up with an idea for how to do this efficiently, and so
far, I have not had any inspirations.

So, can anyone tell me the basic idea I need to get this to work?  I'm
sure it'll be obvious once someone tells me :-).

Thanks,

  Jonathan Kamens

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