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Re: NAND technical review
- From: Ross Younger <wry at ecoscentric dot com>
- To: Jonathan Larmour <jifl at jifvik dot org>
- Cc: Rutger Hofman <rutger at cs dot vu dot nl>, eCos developers <ecos-devel at ecos dot sourceware dot org>
- Date: Tue, 10 Nov 2009 10:38:14 +0000
- Subject: Re: NAND technical review
- References: <4ACB4B58.2040804@ecoscentric.com> <4ACC61F0.3020303@televic.com> <4AD3E92E.5020301@jifvik.org> <4AD47ADE.9010606@cs.vu.nl> <4AD6A7EC.8080703@jifvik.org> <4ADC452B.5040706@ecoscentric.com> <4ADD14E1.3050702@jifvik.org> <4ADD8E47.1080305@ecoscentric.com> <4ADE6C92.9060300@jifvik.org> <4AE02E54.7000508@ecoscentric.com> <4AF8F6D7.1000709@jifvik.org>
> [syndrome]
> So can you just confirm that (E) supports that form of hardware ECC
> implementation?
I've just googled up the outline of syndrome mode (which seems,
incidentally, to be at least a de facto standard term). I don't see any
reason I couldn't fit it in given my current hooks.
> I also note
> with the SAM9260 that the hardware ECC registers get wiped if you start
> to read/write another page, so can you confirm or otherwise that no
> other NAND API user can cause that to happen in (E)?
The standard per-device locking provided by (E) will take care of this. If
there is a risk of concurrent access to other devices causing problems it's
trivial to add a further board-level lock in the driver.
> The SAM9260 also
> requires you to read the entire page data, followed immediately by the
> spare area locations where the ECC is stored. Is that also supportable
> by (E)?
It looks like that's standard for syndrome-type ECC. I think this is just a
funny OOB area layout, though as ever I'd have to try it and see to be sure.
Ross
(PS. BTW, I am still working on that fresh anon-based drop I promised the
other week, but am trying to find out why the benchmarks are so screwy on
the EA LPC2468 before I finish cutting the drop. And - speaking of ECC -
sitting in my pile of queued commits I have a major speed-up in software ECC
calculation...)
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