Re: [ECOS] interrupt latency (ARM7)

[Ilko Iliev <iliev at caretec dot at>]

At 08:22 10/17/2001 +0900, you wrote:
>On Wed, 2001-10-17 at 06:41, Jonathan Larmour wrote:
>> Ilko Iliev wrote:
>> > 
>> > I have custom board with ARM7 (AT91M55800) at 33Mhz system CPU clock.
>> > 
>> > I measured ISR handling latency time 48-90 mkSec.
>> > 
>> > It is normal???
>> 
>> Maybe; it depends on a whole lot of things like speed of RAM, speed of ROM
>> (if you're running from ROM) and the settings of quite a few options in the
>> eCos configuration. I can guarantee it could be reduced by using different
>> configuration options; the default configuration is not the fastest!
>
>Other things can affect this greatly.
>  * Does this system run from ROM/FLASH or RAM?
>  * Does the CPU have caches?  what size?  are they enabled?
>
>Many of the "simpler" ARM7 device cores do not have any caches which 
>serverly impacts their performance.
>
>Just a few things to think about.

The AT91M55800 has no cache.
The system run in RAM - 16bit, 90ns ( 3WaitStates). The ROM is 16bit, 90ns too.
The tick interrupt is every 1 ms.
I use JEENI with gdb (insight) - the "Rom monitor support" is disabled.

I measured IRS latency again - it is 5 - 60 mkSec.
5 mkSec is the minimum - there are 55 instructions before the interrupt handler.

Why are the interrupts so long time disabled?
Why the system disable FIQ too?
Haw can I reduce the ISR latency time?
I need a interrupt every 100mkSec continuous (unbroken). How I make this?


best regards
Ilko