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Re: powerpc serial driver
Christoph Csebits wrote:
>
> On Thu, Nov 29, 2001 at 04:34:42AM +0000, Jonathan Larmour wrote:
> > If quicc_smc1_txbuf isn't aligned, then it won't be
> > CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_TxSIZE long any more.
>
> You are right, i forgot to change some lines before diff.
> patch enclosed.
I made a few more changes. In particular, using HAL_DCACHE_LINE_SIZE (which
is 16!) instead of a hard-coded 32.
> > Also, got a ChangeLog entry?
>
> Is this the way ChangeLog entries are usually made?
Yep, that's fine, thanks! I've checked this in.
Jifl
Index: src/quicc_smc_serial.c
===================================================================
RCS file:
/home/cvs/ecc/ecc/devs/serial/powerpc/quicc/current/src/quicc_smc_serial.c,v
retrieving revision 1.6
diff -u -5 -p -r1.6 quicc_smc_serial.c
--- src/quicc_smc_serial.c 2000/12/22 15:46:09 1.6
+++ src/quicc_smc_serial.c 2001/11/30 16:07:03
@@ -52,10 +52,13 @@
#include <cyg/hal/hal_cache.h>
#include CYGBLD_HAL_PLATFORM_H
#ifdef CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC
+// macro for aligning buffers to cache lines
+#define ALIGN_TO_CACHELINES(b) ((cyg_uint8 *)(((CYG_ADDRESS)(b) +
(HAL_DCACHE_LINE_SIZE-1)) & ~(HAL_DCACHE_LINE_SIZE-1)))
+
// Buffer descriptor control bits
#define QUICC_BD_CTL_Ready 0x8000 // Buffer contains data (tx) or is
empty (rx)
#define QUICC_BD_CTL_Wrap 0x2000 // Last buffer in list
#define QUICC_BD_CTL_Int 0x1000 // Generate interrupt when empty (tx)
or full (rx)
#define QUICC_BD_CTL_MASK 0xB000 // User settable bits
@@ -152,12 +155,12 @@ static SERIAL_CHANNEL(quicc_smc_serial_c
CYG_SERIAL_WORD_LENGTH_DEFAULT,
CYG_SERIAL_FLAGS_DEFAULT
);
#endif
-static unsigned char
quicc_smc1_txbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_TxNUM][CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_TxSIZE];
-static unsigned char
quicc_smc1_rxbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_RxNUM][CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_RxSIZE];
+static unsigned char
quicc_smc1_txbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_TxNUM][CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_TxSIZE
+ HAL_DCACHE_LINE_SIZE-1];
+static unsigned char
quicc_smc1_rxbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_RxNUM][CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_RxSIZE
+ HAL_DCACHE_LINE_SIZE-1];
DEVTAB_ENTRY(quicc_smc_serial_io1,
CYGDAT_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_NAME,
0, // Does not depend on a lower level
interface
&cyg_io_serial_devio,
@@ -196,12 +199,12 @@ static SERIAL_CHANNEL(quicc_smc_serial_c
CYG_SERIAL_PARITY_DEFAULT,
CYG_SERIAL_WORD_LENGTH_DEFAULT,
CYG_SERIAL_FLAGS_DEFAULT
);
#endif
-static unsigned char
quicc_smc2_txbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_TxNUM][CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_TxSIZE];
-static unsigned char
quicc_smc2_rxbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_RxNUM][CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_RxSIZE];
+static unsigned char
quicc_smc2_txbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_TxNUM][CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_TxSIZE
+ HAL_DCACHE_LINE_SIZE-1];
+static unsigned char
quicc_smc2_rxbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_RxNUM][CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_RxSIZE
+ HAL_DCACHE_LINE_SIZE-1];
DEVTAB_ENTRY(quicc_smc_serial_io2,
CYGDAT_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_NAME,
0, // Does not depend on a lower level
interface
&cyg_io_serial_devio,
@@ -396,15 +399,15 @@ quicc_smc_serial_init(struct cyg_devtab_
&eppc->pram[2].scc.pothers.smc_modem.psmc.u, // PRAM
&eppc->smc_regs[0], // Control
registers
TxBD,
CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_TxNUM,
CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_TxSIZE,
- &quicc_smc1_txbuf[0][0],
+
ALIGN_TO_CACHELINES(&quicc_smc1_txbuf[0][0]),
RxBD,
CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_RxNUM,
CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_RxSIZE,
- &quicc_smc1_rxbuf[0][0],
+
ALIGN_TO_CACHELINES(&quicc_smc1_rxbuf[0][0]),
0xC0, // PortB mask
CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_BRG,
12 // SI mask position
);
TxBD = RxBD + CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_RxNUM*8;
@@ -428,15 +431,15 @@ quicc_smc_serial_init(struct cyg_devtab_
&eppc->pram[3].scc.pothers.smc_modem.psmc.u, // PRAM
&eppc->smc_regs[1], // Control
registers
TxBD,
CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_TxNUM,
CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_TxSIZE,
- &quicc_smc2_txbuf[0][0],
+
ALIGN_TO_CACHELINES(&quicc_smc2_txbuf[0][0]),
RxBD,
CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_RxNUM,
CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_RxSIZE,
- &quicc_smc2_rxbuf[0][0],
+
ALIGN_TO_CACHELINES(&quicc_smc2_rxbuf[0][0]),
0xC00, // PortB mask
CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_BRG,
28 // SI mask position
);
#endif
@@ -473,10 +476,17 @@ quicc_smc_serial_lookup(struct cyg_devta
// Force the current transmit buffer to be sent
static void
quicc_smc_serial_flush(quicc_smc_serial_info *smc_chan)
{
volatile struct cp_bufdesc *txbd = smc_chan->txbd;
+ int cache_state;
+
+ HAL_DCACHE_IS_ENABLED(cache_state);
+ if (cache_state) {
+ HAL_DCACHE_FLUSH(txbd->buffer, smc_chan->txsize);
+ }
+
if ((txbd->length > 0) &&
((txbd->ctrl & (QUICC_BD_CTL_Ready|QUICC_BD_CTL_Int)) == 0)) {
txbd->ctrl |= QUICC_BD_CTL_Ready|QUICC_BD_CTL_Int; // Signal
buffer ready
if (txbd->ctrl & QUICC_BD_CTL_Wrap) {
txbd = smc_chan->tbase;
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