RE: [ECOS] how breakpoint instruction execute

["Robert Cragie" <rcc at jennic dot com>]

As a rule, yes, but it depends on your target processor.

Multi-ICE is a JTAG based debugger which communicates with a debug unit on
the ARM core using the DCC (Debug Comms Channel). The debug unit is present
in chips whose ARM core has a 'D' in the suffix (e.g. ARM7TDMI - arm7tDmi).
The debug unit on these devices have something called an 'icebreaker' on
them, which allows setting of two hardware breakpoints. These could be in
ROM. However, further breakpoints must be done using a software interrupt
(SWI); this is called 'semihosting'. ARM9TDMI processors also have 'vector
catch' circuitry in the debug unit, which changes the breakpoint/watchpoint
allocation procedure.

So you may be able to do some limited breakpoint setting with code which is
in ROM, but if it is in RAM, there will be no such restrictions.

I suggest you read the accompanying documentation with the Multi-ICE for the
complete (fairly complex) picture.

Robert Cragie, Design Engineer
________________________________________________________
Jennic Ltd, Furnival Street, Sheffield, S1 4QT,  UK
www.jennic.com  Tel: +44 (0) 114 281 2655

> -----Original Message-----
> From: Raghunandan [mailto:raghunandan@inablers.net]
> Sent: 12 July 2002 10:05
> To: Robert Cragie
> Subject: Re: [ECOS] how breakpoint instruction execute
>
>
> Hi.
>  If i use GDB and the multi-ice support provided by redhat do i still need
> to run in RAM mode.
>
> Raghu
> ----- Original Message -----
> From: "Robert Cragie" <rcc@jennic.com>
> To: "zhlg_shuhan" <zhlg_shuhan@sina.com>;
> <ecos-discuss@sources.redhat.com>
> Sent: Thursday, July 11, 2002 3:08 PM
> Subject: RE: [ECOS] how breakpoint instruction execute
>
>
> > Assuming you are running a debugger like GDB with some sort of monitor:
> >
> > * Via the monitor, the debugger saves the opcode at the breakpoint and
> > replaces it with a trap, or software interrupt.
> > * When execution reaches the trap, an exception handler is called which
> > communicates with the debugger to indicate that the breakpoint has been
> > reached. The debugger may resume execution if the breakpoint is
> conditional.
> > * When the breakpoint is removed, the debugger will restore the
> opcode at
> > the breakpoint via the monitor.
> >
> > This explains why code which needs breakpoints typically needs to run in
> > RAM, and why execution with conditional breakpoints doesn't run in real
> > time.
> >
> > Things may be different if you are using JTAG-based debuggers or an ICE
> > (In-Circuit-Emulator) based debugger.
> >
> > Robert Cragie, Design Engineer
> > ________________________________________________________
> > Jennic Ltd, Furnival Street, Sheffield, S1 4QT,  UK
> > www.jennic.com  Tel: +44 (0) 114 281 2655
> >
> > > -----Original Message-----
> > > From: ecos-discuss-owner@sources.redhat.com
> > > [mailto:ecos-discuss-owner@sources.redhat.com]On Behalf Of zhlg_shuhan
> > > Sent: 11 July 2002 07:51
> > > To: ecos-discuss@sources.redhat.com
> > > Subject: [ECOS] how breakpoint instruction execute
> > >
> > >
> > > How breakpoint instruction executes on run-time debug?
> > >
> > > 3x!
> > > ______________________________________
> > >
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> >
> >
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> >
> >
>
>
>


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