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MPC8xx FEC Ethernet driver bugfixes/improvements


Hi,

i am working on a MPC860 based, custom designed board, using the FEC
Ethernet driver (originally written for the VIPER)

I encountered some problems in the file if_fec.c:

1. Datacache SYNCS are performed, regardless wether the cache is enabled
or not.
2. The offsetaddress of the FEC-bufferdescriptors is hardcoded in
if_fec.c.
   For some applications / targets that heavily use internal memory for
buffers
   or bufferdescriptors, the FEC-BDs can be in the way. It would be
better to
   define this address in the platform-specific code (like e.g.
viper_eth.inl)
3. Most importand: During initialisation the datacache is disabled but
not
   re-enabled.

The following patch should fix these problems:

Index: if_fec.c
===================================================================
RCS file:
/cvs/ecos/ecos/packages/devs/eth/powerpc/fec/current/src/if_fec.c,v
retrieving revision 1.10
diff -u -r1.10 if_fec.c
--- if_fec.c	3 Sep 2002 16:56:14 -0000	1.10
+++ if_fec.c	11 Oct 2002 07:46:37 -0000
@@ -159,6 +159,10 @@
 #define FEC_ETH_RESET_PHY()
 #endif
 
+#ifndef FEC_EPPC_BD_OFFSET
+#define FEC_EPPC_BD_OFFSET 0x2C00
+#endif
+
 // LED activity [exclusive of hardware bits]
 #ifndef _get_led
 #define _get_led()  
@@ -263,7 +267,8 @@
 
     // Ensure consistent state between cache and what the FEC sees
     HAL_DCACHE_IS_ENABLED(cache_state);
-    HAL_DCACHE_SYNC();
+    if (cache_state)
+      HAL_DCACHE_SYNC();
     HAL_DCACHE_DISABLE();
 
     // Shut down ethernet controller, in case it is already running
@@ -285,7 +290,7 @@
 
 #define ROUNDUP(b,s) (((unsigned long)(b) + (s-1)) & ~(s-1))
 #ifdef FEC_USE_EPPC_BD
-    txbd = (struct fec_bd *)(0x2C00 + (cyg_uint32)eppc);
+    txbd = (struct fec_bd *)(FEC_EPPC_BD_OFFSET + (cyg_uint32)eppc);
     rxbd = &txbd[CYGNUM_DEVS_ETH_POWERPC_FEC_TxNUM];
 #else
     txbd = fec_eth_txring;
@@ -398,7 +403,8 @@
 
     // Ensure consistent state between cache and what the FEC sees
     HAL_DCACHE_IS_ENABLED(cache_state);
-    HAL_DCACHE_SYNC();
+    if (cache_state)
+      HAL_DCACHE_SYNC();
     HAL_DCACHE_DISABLE();
 
     qi->fec = fec;
@@ -498,6 +504,9 @@
     // Initialize upper level driver
     (sc->funs->eth_drv->init)(sc, (unsigned char *)&enaddr);
     
+    if (cache_state)
+      HAL_DCACHE_ENABLE();
+
     return true;
 }
  

Wolfgang

-- 
Wolfgang Heppner

High Speed Kamerasysteme  - Abt. Bildsensorik (ESY-B)
High Speed Camera Systems - Dept. Electronic Imaging (ESY-B)

Fraunhofer                            
Institut Integrierte Schaltungen
Angewandte Elektronik

Am Wolfsmantel 33 
91058 Erlangen       
(Germany)

Tel:   +49 (0) 9131 776 528
Fax:   +49 (0) 9131 776 598

email: hep@iis.fhg.de
web:   http://www.iis.fhg.de

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