[ECOS] structure XScale HAL ?

[david at mind dot be]

Hello,

I was wondering if anybody else has been using the xscale HAL for a port other
than the IQ-80321 ?
Or has this been a one-off implementation for the IQ-80321 ?
As I am currently doing a port to a pxa-250 based board, I have been dissecting
the xscale tree a bit, and I think that the current structure of the xscale
tree needs some rearranging, so I would appreciate some feedback on the following:

Currently, CYGPKG_HAL_ARM_XSCALE_IQ80321 has CYGPKG_HAL_ARM_XSCALE_CORE as its
parent. But the IQ-80321 is a board based on the IOP321 cpu, which in turn has
an XScale core.
Similarly, the port I am doing is for a board based on the PXA250 cpu, which also has an XScale core.
So, to have a clean port, I think it would be best to have a 3-level
structure instead of the current 2-level structure:
- XSCALE_CORE (with core specific stuff)
- XSCALE_PXA250 (with cpu specific stuff)
- XSCALE_my_board (with board specific stuff)

With the current 2-level structure of the IQ-80321 port, the cpu-support
for the IOP321 gets mixed with the board-support for the IQ-80321, which also
means that the IOP321 specific stuff cannot be easily used for other ports
with that same cpu.
I think it would also be nice to have separate directories in the tree for
this (e.g. xscale/core , xscale/cpu, xscale/board).

But before starting with that structure for my port, I would like to know what
anybody else is doing. 
(If it's a daft idea, I will also stick to the 2-level structure ;-)

Best Regards,
David

-- 
Before posting, please read the FAQ: http://sources.redhat.com/fom/ecos
and search the list archive: http://sources.redhat.com/ml/ecos-discuss