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Help with Redboot an a ARM SA1100 Lart Board
- From: "Steven.Clugston" <Steven dot Clugston at newcastle dot ac dot uk>
- To: ecos-discuss at sources dot redhat dot com
- Date: Fri, 8 Aug 2003 18:32:44 +0100
- Subject: [ECOS] Help with Redboot an a ARM SA1100 Lart Board
I am trying to get ecos running on a SA1100 variant board called a 'Lart' from
http://www.lart.tudelft.nl/
I have used a setup based on the Brutus template as I cannot get the sa1100mm
template to work at all. The lart comes with a custom boot loader called blob
that lets you run linux from flash ram. The board has 4Mb of Intel 28F160F3
flash ram and 32Mb of EDO DRAM configured on banks 0 and one only. It has no
SRAM or any other memory.
The blob boot loader reports the memory as follows:
Memory map:
0x00800000 @ 0xC0000000 (8 MB)
0x00800000 @ 0xC1000000 (8 MB)
0x00800000 @ 0xC8000000 (8 MB)
0x00800000 @ 0xC9000000 (8 MB)
I don't really understand why the memory is fragmented into 8Mb blocks and not
two continuous blocks of 16Mb per bank with an offset of 128Mb from the base
of each bank, but it works with the supplied linux setup and I have used the
DRAM and flash waveform/config register settings from the blob loader and put
them into the platform_setup.h in place of the brutus ones. I have edited the
assembly to make sure that the same actual values are being passed to the
registers as the blob loader.
My problem is that when I try to upload then run code from reboot (running
from ROM)it either hangs from the go command (using the brutus memory config)
or gives no output except a "$T0a0f:e47e0040;0d:c0a60000;#dc" string everytime
I hit a key in the terminal window when using the blob memory settings. This
same string occurs after tying 'go' or 'go address' regardless of whether I
upload code or not or what ever memory location I try to run it from, as shown
below:
Platform: LART development system (StrongARM 1100)
Copyright (C) 2000, 2001, 2002, Red Hat, Inc.
RAM: 0x00000000-0x02000000, 0x0000d8a8-0x02000000 available
RedBoot> go
$T0a0f:e47e0040;0d:c0a60000;#dc
When I use gdb with -w insight to upload and run the examples such as the
hello world one, it seems to step through the code OK.
Please can anyone help, I have been struggling with this for a week or so. I
have included object dumps of the hello executable and the redboot rom image,
and also the memory mapping I have tried to use in various platform sepecific
files.
$ arm-elf-objdump -h hello
hello: file format elf32-littlearm
Sections:
Idx Name Size VMA LMA File off Algn
0 .debug_aranges 00001c40 00000000 00000000 00016f60 2**0
CONTENTS, READONLY, DEBUGGING
1 .debug_pubnames 00004445 00000000 00000000 00018ba0 2**0
CONTENTS, READONLY, DEBUGGING
2 .debug_info 0009cb44 00000000 00000000 0001cfe5 2**0
CONTENTS, READONLY, DEBUGGING
3 .debug_abbrev 0000f56e 00000000 00000000 000b9b29 2**0
CONTENTS, READONLY, DEBUGGING
4 .debug_line 0001f9f1 00000000 00000000 000c9097 2**0
CONTENTS, READONLY, DEBUGGING
5 .debug_frame 00004eac 00000000 00000000 000e8a88 2**2
CONTENTS, READONLY, DEBUGGING
6 .debug_str 0000a8b5 00000000 00000000 000ed934 2**0
CONTENTS, READONLY, DEBUGGING
7 .fixed_vectors 00000140 00000020 00000020 000f8200 2**5
CONTENTS, READONLY
8 .rom_vectors 00000040 00010000 00010000 00008000 2**0
CONTENTS, ALLOC, LOAD, READONLY, CODE
9 .text 0000bbcc 00010040 00010040 00008040 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
10 .fini 00000000 0001bc0c 0001bc0c 000f8340 2**0
CONTENTS
11 .rodata 00002e83 0001bc0c 0001bc0c 00013c0c 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
12 .rodata1 00000000 0001ea90 0001ea90 000f8340 2**0
CONTENTS
13 .fixup 00000000 0001ea90 0001ea90 000f8340 2**0
CONTENTS
14 .gcc_except_table 00000000 0001ea90 0001ea90 000f8340 2**0
CONTENTS
15 .data 000004d0 0001ea90 0001ea90 00016a90 2**2
CONTENTS, ALLOC, LOAD, DATA
16 .bss 00004484 0001ef60 0001ef60 00016f60 2**5
ALLOC
17 .debug_ranges 00000778 00000000 00000000 000f8340 2**0
CONTENTS, READONLY, DEBUGGING
redboot.elf: file format elf32-littlearm
Sections:
Idx Name Size VMA LMA File off Algn
0 .debug_aranges 00001008 00000000 00000000 00018664 2**0
CONTENTS, READONLY, DEBUGGING
1 .debug_pubnames 00001d1f 00000000 00000000 0001966c 2**0
CONTENTS, READONLY, DEBUGGING
2 .debug_info 0001e70b 00000000 00000000 0001b38b 2**0
CONTENTS, READONLY, DEBUGGING
3 .debug_abbrev 00004be0 00000000 00000000 00039a96 2**0
CONTENTS, READONLY, DEBUGGING
4 .debug_line 0001043c 00000000 00000000 0003e676 2**0
CONTENTS, READONLY, DEBUGGING
5 .debug_frame 00002a88 00000000 00000000 0004eab4 2**2
CONTENTS, READONLY, DEBUGGING
6 .debug_str 000047b8 00000000 00000000 0005153c 2**0
CONTENTS, READONLY, DEBUGGING
7 .rom_vectors 00000040 40000000 40000000 00008000 2**0
CONTENTS, ALLOC, LOAD, READONLY, CODE
8 .text 0000c63c 40000040 40000040 00008040 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
9 .fini 00000000 4000c67c 4000c67c 00055cf4 2**0
CONTENTS
10 .rodata 0000177c 4000c67c 4000c67c 0001467c 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
11 .rodata1 00000000 4000ddf8 4000ddf8 00055cf4 2**0
CONTENTS
12 .fixup 00000000 4000ddf8 4000ddf8 00055cf4 2**0
CONTENTS
13 .gcc_except_table 00000000 4000ddf8 4000ddf8 00055cf4 2**0
CONTENTS
14 .fixed_vectors 00000140 00000020 00000020 00055d00 2**5
CONTENTS, READONLY
15 .data 00000664 00008000 4000ddf8 00018000 2**2
CONTENTS, ALLOC, LOAD, DATA
16 .bss 00005240 00008664 00008664 00000664 2**5
ALLOC
17 .debug_ranges 00000678 00000000 00000000 00055e40 2**0
CONTENTS, READONLY, DEBUGGING
>From plf_mmap.h
#define HAL_VIRT_TO_PHYS_ADDRESS( vaddr, paddr ) CYG_MACRO_START \
cyg_uint32 _v_ = (cyg_uint32)(vaddr); \
if ( 8 * SZ_1M > _v_ ) /* 8Mb of DRAM Bank 0 from 0-8Mb */ \
_v_ += 0xc00u * SZ_1M; \
if ( 16 * SZ_1M > _v_ ) /* 8Mb of DRAM Bank 0 from 8-16Mb */ \
_v_ += (0xc10u * SZ_1M) - (8 * SZ_1M); \
if ( 24 * SZ_1M > _v_ ) /* 8Mb of DRAM Bank 1 from 16-24Mb */ \
_v_ += (0xc80u * SZ_1M) - (16 * SZ_1M); \
if ( 32 * SZ_1M > _v_ ) /* 8Mb of DRAM Bank 1 from 24-32M */ \
_v_ += (0xc90u * SZ_1M) - (24 * SZ_1M); \
else if ( 0x400u * SZ_1M > _v_ ) /* Space between RAM and mapped ROM */\
/* no change */ ; \
else if ( 0x401u * SZ_1M > _v_ ) /* Mapped boot ROM size 1Mb */ \
_v_ -= 0x400u * SZ_1M; \
else /* Rest of it */ \
/* no change */ ; \
(paddr) = _v_; \
CYG_MACRO_END
#define HAL_PHYS_TO_VIRT_ADDRESS( paddr, vaddr ) CYG_MACRO_START \
cyg_uint32 _p_ = (cyg_uint32)(paddr); \
if ( 4 * SZ_1M > _p_ ) /* 4Mb Boot ROM mapped to 0x400Mb */ \
_p_ += 0x400u * SZ_1M; \
else if ( 0xc00u * SZ_1M > _p_ ) /* Space between ROM and DRAM */ \
/* no change */ ; \
else if ( 0xc08u * SZ_1M > _p_ ) /* Raw RAM bank 0, 8Mb at 0xc00 */ \
_p_ -= 0xc00u * SZ_1M; \
else if ( 0xc10u * SZ_1M > _p_ ) /* Space between DRAM 0 blocks */ \
/* no change */ ; \
else if ( 0xc18u * SZ_1M > _p_ ) /* Raw RAM bank 0, 8Mb at 0xc10 */ \
_p_ -= (0xc10u * SZ_1M) + (8 * SZ_1M); \
else if ( 0xc80u * SZ_1M > _p_ ) /* Space between DRAM banks */ \
/* no change */ ; \
else if ( 0xc88u * SZ_1M > _p_ ) /* Raw RAM bank 1, 8Mb at 0xc80 */ \
_p_ -= (0xc80u * SZ_1M) + (16 * SZ_1M); \
else if ( 0xc90u * SZ_1M > _p_ ) /* Space between SDRAM banks */ \
/* no change */ ; \
else if ( 0xc98u * SZ_1M > _p_ ) /* Raw RAM bank 1, 8Mb at 0xc90 */ \
_p_ -= (0xc90u * SZ_1M) + (24 * SZ_1M); \
else /* Rest of it */ \
/* no change */ ; \
(vaddr) = _p_ ; \
CYG_MACRO_END
>From lart_misc.c
/* Actual Virtual Size Attributes
Function */
/* Base Base MB cached? buffered?
access permissions */
/* xxx00000 xxx00000
*/
X_ARM_MMU_SECTION(0x000, 0x400, 4, ARM_CACHEABLE, ARM_BUFFERABLE,
ARM_ACCESS_PERM_RW_RW); /* Boot flash ROMspace */
X_ARM_MMU_SECTION(0x800, 0x800, 0x400, ARM_UNCACHEABLE,
ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* StrongARM(R) Registers */
X_ARM_MMU_SECTION(0xC00, 0x000, 8, ARM_CACHEABLE, ARM_BUFFERABLE,
ARM_ACCESS_PERM_RW_RW); /* DRAM Bank 0 */
X_ARM_MMU_SECTION(0xC10, 0x008, 8, ARM_CACHEABLE, ARM_BUFFERABLE,
ARM_ACCESS_PERM_RW_RW); /* DRAM Bank 0 */
X_ARM_MMU_SECTION(0xC80, 0x010, 8, ARM_CACHEABLE, ARM_BUFFERABLE,
ARM_ACCESS_PERM_RW_RW); /* DRAM Bank 1 */
X_ARM_MMU_SECTION(0xC90, 0x008, 8, ARM_CACHEABLE, ARM_BUFFERABLE,
ARM_ACCESS_PERM_RW_RW); /* DRAM Bank 1 */
X_ARM_MMU_SECTION(0xC00, 0xC00, 256, ARM_UNCACHEABLE, ARM_BUFFERABLE,
ARM_ACCESS_PERM_RW_RW); /* DRAM Banks - raw access */
X_ARM_MMU_SECTION(0xE00, 0xE00, 128, ARM_CACHEABLE, ARM_BUFFERABLE,
ARM_ACCESS_PERM_RW_RW); /* Zeros (Cache Clean) Bank */
--
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