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Re: Fwd: Packet size limit on TCP/IP stack ?


> mohanlal jangir wrote:
> >
> >         OUTL(VIRT_TO_BUS(p_txcb), ioaddr + SCBPointer);
> >         OUTW(CU_START, ioaddr + SCBCmd);
> >
> > when I see data starting from p_txcb I find it correct in both cases
(first
> > sending total packet size less then or equal to160 and later total
packet
> > size more than 160). This are first 16 bytes starting from p_txcb for
total
> > packet length of 200. (by total packet length, I mean including
ethernet, ip
> > headers)
> > (gdb)x/16xb p_txcb
> > 0xf333cc: 0x00 0x00 0x04 0xe0 0xcc 0x3c 0xf3 0x80
> > 0xf33cd4: 0xff 0xff 0xff 0xff 0xc8 0x80 0x10 0x00
> > (gdb)p /x p_txcb
> > 0xf33ccc
> >
> > pressing command next at line OUTW(CU_START, ioaddr + SCBCmd) sends
packet
> > out if  packet length is less than 160 but does not send if packet lengh
is
> > more than 160. Is it possible that addresses (p_txcb + 160) onwards are
> > somehow invalid?
>
> Certainly could... you should examine your PCI window setup. InitTxRing()
> allocates these buffers from the PCI window. Perhaps the memory is
> corrupted, or overlaps with something else. i.e. look at
> CYGHWR_INTEL_I82559_PCI_MEM_MAP_SIZE and
> CYGHWR_INTEL_I82559_PCI_MEM_MAP_BASE. And of course your MMU setup (see if
> there are any special properties of the address at (start of packet +
160).
>
> Jifl

PCI window memory seems to be ok. This is snapshot of target.ld
MEMORY
{
       ram : ORIGIN = 0, LENGTH = 0x01000000
}

__pci_window = 0xf00000; . = __pci_window + 0x100000;

CYGHWR_INTEL_I82559_PCI_MEM_MAP_BASE is initialized to
CYGARC_PHYSICAL_ADDRESS(CYG_LABEL_NAME(__pci_window)) and
CYGHWR_INTEL_I82559_PCI_MEM_MAP_SIZE is 0x100000. InitTxRing allocates
memory from this space. I have also enabled assert to see if PCI window is
going out of bounds but that never asserts.
MMU macros are as follows:
#define  CYGHWR_INTEL_I82559_PCI_VIRT_TO_BUS( _x_ )  (((cyg_uint32)( _x_ ))
| INTEGRATOT_HDR0_SDRAM_BASE)
#define CYGHWR_INTEL_I82559_PCI_BUS_TO_VIRT ( _x_ )  (((cyg_uint32( ( _x_ ))
& ~ INTEGRATOT_HDR0_SDRAM_BASE)

INTEGRATOT_HDR0_SDRAM_BASE is defined to 0x80000000. This seems to be  ok
for packets of size 160 as well as 160+.
I enabled DEBUG macro for i82559.c. Driver seems to working fair. All the
packets are transmitted well by driver but only packets having length less
than 160 are reaching to other end. Apparently there is no problem in
receiving packet of length more than 160. Problem occurs at transmission
time only. Any clue in this regard is appreciated.

Regards
Mohanlal

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