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Re: hal/powerpc/arch/current/src/vectors.S
- From: "Gary Thomas" <gary at mlbassoc dot com>
- To: bob dot koninckx at mech dot kuleuven dot ac dot be
- Cc: ecos-discuss at sources dot redhat dot com
- Date: Tue, 28 Oct 2003 01:50:49 -0700 (MST)
- Subject: Re: [ECOS] hal/powerpc/arch/current/src/vectors.S
- References: <1067293541.1407.21.camel@pc-002>
Bob Koninckx said:
> Hi,
>
> Apparently, the following few lines in default interrupt and exception
> vsr of the powerpc architecture have been made conditional. That is,
> lines 474 and following
>
> # Enable MMU.
> lwi r3,CYG_MSR
> sync
> mtmsr r3
> sync
>
> have been changed to
>
> #ifdef CYGHWR_HAL_POWERPC_ENABLE_MMU
> # Enable MMU.
> lwi r3,CYG_MSR
> sync
> mtmsr r3
> sync
> #endif
>
>
> I think this is not correct, since the CYG_MSR macro holds more
> information than just enabling / disabling of the MMU. On the mpc555, it
> is also used to enable / disable the floating point unit. This
> particular processor does not have an MMU. As a consequence, the now
> made conditional code is no longer included in the build. The first
> interrupt therefore causes a floating point unavail exception as soon as
> the floating point registers are stached away.
Indeed, it looks like I was a bit over-exuberant with that change, sorry!
I've reverted it, along with some better comments about what's going on.
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