RE: [ECOS] Anyone run on Intel Xeon processor?

[<kevin_lemay at agilent dot com>]

Nick,

The APIC is enabled by default. This is from the current Intel documentation:

The APIC global enable/disable flag in the IA32_APIC_BASE MSR permits the local APIC to be permanently disabled. Following a power-up or reset, this flag is set, enabling the local APIC. To permanently disable the local APIC until the next power-up or reset, software can clear this flag. When this flag is clear, the processor is functionally equivalent to an IA-32 processor without an on-chip APIC (for example, an Intel486 processor). In this state, CPUID feature flag for the APIC (bit 9 for the EDX register [see Section 8.4.2., "Presence of the Local APIC"]) is set to 0. Also, when the APIC global enable/disable flag in the IA32_APIC_BASE MSR flag has been cleared, it can only be reset by a power-up or RESET action.

I am going to disable it in hal_cpu_init (in pcmb.inc) if the SMP support is not selected. This should make everthing work.

The disable bit is in a MSR register. I do not need the address of the APIC to disable it.

Kevin
-----Original Message-----
From: nickg@miso.calivar.com [mailto:nickg@miso.calivar.com]On Behalf Of
Nick Garnett
Sent: Tuesday, February 10, 2004 11:28 AM
To: LEMAY,KEVIN (A-Roseville,ex1)
Cc: ecos-discuss@sources.redhat.com
Subject: Re: [ECOS] Anyone run on Intel Xeon processor?


<kevin_lemay@agilent.com> writes:

> Nick,
> 
> I have made more progress on this... I found your debug code and
> have been turning things on and adding more as needed.
> 
> It is stalling in the code that starts the other processors. What I
> really wanted fixed is the interrupt processing for Xeons, which
> appeared to be coded if the SMP support was added.
> 
> There is a master enable/disable bit for the APIC. The documentation
> says that it will run like a pentium 4 if this bit is set to zero. I
> am going to try that for now. I may submit it back to the group if
> it works. I am not ready to redo all of the SMP support, I really
> don't need it anyway.

Shouldn't the interrupt controller default to the standard PIC
interface? This is normally used for single processors. What are you
doing that needs the APIC?

If you really need the APIC, the best approach would be to try and
make the APIC support an independent config option from the SMP
stuff. SMP will still enable it, but it should also be settable
independently.

The only real problem with that is that the locations of the APICs and
IOAPIC is read from the MP structure. So you may have to fake that.

-- 
Nick Garnett                    eCos Kernel Architect
http://www.ecoscentric.com      The eCos and RedBoot experts


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