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Problems with interrupt and RTC on AT91EB40A -update +solution
- From: "Martin" <msie02 at control dot auc dot dk>
- To: <ecos-discuss at sources dot redhat dot com>
- Date: Wed, 16 Jun 2004 13:07:00 +0200
- Subject: [ECOS] Problems with interrupt and RTC on AT91EB40A -update +solution
-----Original Message-----
From: ecos-discuss-owner@ecos.sourceware.org
[mailto:ecos-discuss-owner@ecos.sourceware.org] On Behalf Of Martin
Sent: 18. maj 2004 18:17
To: ecos-discuss@sources.redhat.com
Subject: [ECOS] Problems with interrupt and RTC on AT91EB40A
I have just plugged in a completely new EB40A board and can not use
functions as cyg_thread_delay and alarm handlers. If I try to sample the
system clock repeatedly with cyg_real_time_clock, I get the same result/time
every try.
I suggest that the hardware clock does not generate interrupts, but is this
not standard?
The ecos tree is built from configtool with standard configuration for
EB40A.
I have not manually disabled any interrupts in my code (trying to just
basicly making the twothreads.c example run).
Any ideas for me to try are more than welcome.
Regards,
Martin
Update:
When I choose the eCos template related to EB40A I get a conflict:
Item: CYKPKG_HAL_ARM_AT91_EB40A, Conflict: unsatisfied, Property: Requires
CYGHWR_HAL_ARM_AT91 == "R40008"
Proposed Solutions:
Item: CYGHWR_HAL_ARM_AT91, Value R40008
Item: CYGNUM_HAL_RTC_PERIOD, Value 20625
Item: CYGNUM_HAL_ARM_AT91_CLOCK_SPEED, Value 66000000
Is this a problem? If I do not choose to solve the conflicts, eCos will not
build.
Martin
Problem solved.
The problem was that the timer counter 0 (TC0) in the ARM7TDMI processer was
not enabled, i.e. it was not running.
A solution to the problem is to modify two files plf_io.h and at91_misc.c
and then rebuild. This was inspired by
http://sources.redhat.com/ml/ecos-discuss/2003-02/msg00272.html, but changes
made there was compliant with an older CVS version. I have attached the two
modified files as we use them, and if changes to the original files in CVS
are made later on, then look through the changes made by me and take what is
needed. The changes are shown between
// Begin Antenna2k4 changes
...Code...
// End Antenna2k4 changes
I have tried to use the timer0 on two new AT91EB40A evaluation kits, and
both of them were not able to start timer0, before the changes was made.
Regards,
Martin
/*==========================================================================
//
// at91_misc.c
//
// HAL misc board support code for Atmel AT91
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
// Copyright (C) 2003 Nick Garnett <nickg@calivar.com>
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): gthomas
// Contributors: gthomas, jskov, nickg, tkoeller, jjung, jbork
// Date: 2001-07-12
// Purpose: HAL board support
// Description: Implementations of HAL board interfaces
// Modification: Modified according to Sensitron example to fit current CVS
version. All changes are shown inside // Begin/End Antenna2k4 changes
//
//####DESCRIPTIONEND####
//
//========================================================================*/
#include <pkgconf/hal.h>
#include <cyg/infra/cyg_type.h> // base types
#include <cyg/infra/cyg_trac.h> // tracing macros
#include <cyg/infra/cyg_ass.h> // assertion macros
#include <cyg/hal/hal_io.h> // IO macros
#include <cyg/hal/hal_arch.h> // Register state info
#include <cyg/hal/hal_diag.h>
#include <cyg/hal/hal_intr.h> // necessary?
#include <cyg/hal/hal_cache.h>
#include <cyg/hal/hal_if.h> // calling interface
#include <cyg/hal/hal_misc.h> // helper functions
#ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
#include <cyg/hal/drv_api.h> // HAL ISR support
#endif
#include <cyg/hal/var_io.h> // platform registers
// Begin Antenna2k4 changes
#include <cyg/hal/plf_io.h> // platform registers
// End Antenna2k4 changes
// -------------------------------------------------------------------------
// Clock support
static cyg_uint32 _period;
void hal_clock_initialize(cyg_uint32 period)
{
CYG_ADDRESS timer = AT91_TC+AT91_TC_TC0;
// Begin Antenna2k4 changes
cyg_uint32 ps_clock_register;
// Enable Timer Counter 0 in Power Save clock enable register
HAL_READ_UINT32(AT91_PS+AT91_PS_PCSR, ps_clock_register);
ps_clock_register &= (AT91_PS_PCER_PIO |
AT91_PS_PCER_US0 |
AT91_PS_PCER_US1);
ps_clock_register |= AT91_PS_PCER_TC0;
HAL_WRITE_UINT32(AT91_PS+AT91_PS_PCER, ps_clock_register);
// End Antenna2k4 changes
CYG_ASSERT(period < 0x10000, "Invalid clock period");
// Disable counter
HAL_WRITE_UINT32(timer+AT91_TC_CCR, AT91_TC_CCR_CLKDIS);
// Set registers
HAL_WRITE_UINT32(timer+AT91_TC_CMR, AT91_TC_CMR_CPCTRG | // Reset counter on CPC
AT91_TC_CMR_CLKS_MCK32); // 1 MHz
HAL_WRITE_UINT32(timer+AT91_TC_RC, period);
// Start timer
HAL_WRITE_UINT32(timer+AT91_TC_CCR, AT91_TC_CCR_TRIG | AT91_TC_CCR_CLKEN);
// Enable timer 0 interrupt
HAL_WRITE_UINT32(timer+AT91_TC_IER, AT91_TC_IER_CPC);
}
void hal_clock_reset(cyg_uint32 vector, cyg_uint32 period)
{
CYG_ADDRESS timer = AT91_TC+AT91_TC_TC0;
cyg_uint32 sr;
CYG_ASSERT(period < 0x10000, "Invalid clock period");
HAL_READ_UINT32(timer+AT91_TC_SR, sr); // Clear interrupt
// Begin Antenna2k4 changes
HAL_INTERRUPT_ACKNOWLEDGE(CYGNUM_HAL_INTERRUPT_RTC);
// End Antenna2k4 changes
if (period != _period) {
hal_clock_initialize(period);
}
_period = period;
}
void hal_clock_read(cyg_uint32 *pvalue)
{
CYG_ADDRESS timer = AT91_TC+AT91_TC_TC0;
cyg_uint32 val;
HAL_READ_UINT32(timer+AT91_TC_CV, val);
*pvalue = val;
}
// -------------------------------------------------------------------------
//
// Delay for some number of micro-seconds
// Use timer #2 in MCLOCK/32 mode.
//
void hal_delay_us(cyg_int32 usecs)
{
CYG_ADDRESS timer = AT91_TC+AT91_TC_TC2;
cyg_uint32 stat;
cyg_uint64 ticks;
// Calculate how many timer ticks the required number of
// microseconds equate to. We do this calculation in 64 bit
// arithmetic to avoid overflow.
ticks = (((cyg_uint64)usecs) * ((cyg_uint64)CYGNUM_HAL_ARM_AT91_CLOCK_SPEED))/32000000LL;
// Disable counter
HAL_WRITE_UINT32(timer+AT91_TC_CCR, AT91_TC_CCR_CLKDIS);
// Set registers
HAL_WRITE_UINT32(timer+AT91_TC_CMR, AT91_TC_CMR_CLKS_MCK32); // 1MHz
HAL_WRITE_UINT32(timer+AT91_TC_RA, 0);
HAL_WRITE_UINT32(timer+AT91_TC_RC, ticks);
// Start timer
HAL_WRITE_UINT32(timer+AT91_TC_CCR, AT91_TC_CCR_TRIG | AT91_TC_CCR_CLKEN);
// Wait for the compare
do {
HAL_READ_UINT32(timer+AT91_TC_SR, stat);
} while ((stat & AT91_TC_SR_CPC) == 0);
}
// -------------------------------------------------------------------------
// Hardware init
void hal_hardware_init(void)
{
unsigned i;
// Set up eCos/ROM interfaces
hal_if_init();
// Reset all interrupts
HAL_WRITE_UINT32(AT91_AIC+AT91_AIC_IDCR, 0xFFFFFFFF);
// Flush internal priority level stack
for (i = 0; i < 8; ++i)
HAL_WRITE_UINT32(AT91_AIC+AT91_AIC_EOI, 0xFFFFFFFF);
}
// -------------------------------------------------------------------------
// This routine is called to respond to a hardware interrupt (IRQ). It
// should interrogate the hardware and return the IRQ vector number.
// Begin Antenna2k4 changes
/*
int hal_IRQ_handler(void)
{
cyg_uint32 irq_num;
cyg_uint32 ivr;
// Calculate active interrupt (updates ISR)
HAL_READ_UINT32(AT91_AIC+AT91_AIC_IVR, ivr);
HAL_READ_UINT32(AT91_AIC+AT91_AIC_ISR, irq_num);
// No valid interrrupt source, treat as spurious interrupt
if (irq_num < CYGNUM_HAL_ISR_MIN || irq_num > CYGNUM_HAL_ISR_MAX)
irq_num = CYGNUM_HAL_INTERRUPT_NONE;
return irq_num;
}
*/
int hal_IRQ_handler(void)
{
cyg_uint32 irq_num;
cyg_uint32 ipr, imr;
HAL_READ_UINT32(AT91_AIC+AT91_AIC_IPR, ipr);
HAL_READ_UINT32(AT91_AIC+AT91_AIC_IMR, imr);
ipr &= imr;
for (irq_num = 0; irq_num < 19; irq_num++) {
if (ipr & (1 << irq_num)) {
break;
}
}
return irq_num;
}
// End Antenna2k4 changes
// -------------------------------------------------------------------------
// Interrupt control
//
void hal_interrupt_mask(int vector)
{
CYG_ASSERT(vector <= CYGNUM_HAL_ISR_MAX &&
vector >= CYGNUM_HAL_ISR_MIN , "Invalid vector");
HAL_WRITE_UINT32(AT91_AIC+AT91_AIC_IDCR, (1<<vector));
}
void hal_interrupt_unmask(int vector)
{
CYG_ASSERT(vector <= CYGNUM_HAL_ISR_MAX &&
vector >= CYGNUM_HAL_ISR_MIN , "Invalid vector");
HAL_WRITE_UINT32(AT91_AIC+AT91_AIC_IECR, (1<<vector));
}
void hal_interrupt_acknowledge(int vector)
{
// Begin Antenna2k4 changes
CYG_ASSERT(vector <= CYGNUM_HAL_ISR_MAX &&
vector >= CYGNUM_HAL_ISR_MIN , "Invalid vector");
HAL_WRITE_UINT32(AT91_AIC+AT91_AIC_ICCR, (1<<vector));
// End Antenna2k4 changes
// No check for valid vector here! Spurious interrupts
// must be acknowledged, too.
HAL_WRITE_UINT32(AT91_AIC+AT91_AIC_EOI, 0xFFFFFFFF);
}
void hal_interrupt_configure(int vector, int level, int up)
{
cyg_uint32 mode;
CYG_ASSERT(vector <= CYGNUM_HAL_ISR_MAX &&
vector >= CYGNUM_HAL_ISR_MIN , "Invalid vector");
if (level) {
if (up) {
mode = AT91_AIC_SMR_LEVEL_HI;
} else {
mode = AT91_AIC_SMR_LEVEL_LOW;
}
} else {
if (up) {
mode = AT91_AIC_SMR_EDGE_POS;
} else {
mode = AT91_AIC_SMR_EDGE_NEG;
}
}
mode |= 7; // Default priority
HAL_WRITE_UINT32(AT91_AIC+(AT91_AIC_SMR0+(vector*4)), mode);
}
void hal_interrupt_set_level(int vector, int level)
{
cyg_uint32 mode;
CYG_ASSERT(vector <= CYGNUM_HAL_ISR_MAX &&
vector >= CYGNUM_HAL_ISR_MIN , "Invalid vector");
CYG_ASSERT(level >= 0 && level <= 7, "Invalid level");
HAL_READ_UINT32(AT91_AIC+(AT91_AIC_SMR0+(vector*4)), mode);
mode = (mode & ~AT91_AIC_SMR_PRIORITY) | level;
HAL_WRITE_UINT32(AT91_AIC+(AT91_AIC_SMR0+(vector*4)), mode);
}
void hal_show_IRQ(int vector, int data, int handler)
{
// UNDEFINED(__FUNCTION__); // FIXME
}
// Begin Antenna2k4 changes
//
// Diagnostic LEDs - there are three colored LEDs which can be used
// to send a simple diagnostic value (8 bits)
//
void
_at91_led(int val)
{
int i, to;
HAL_WRITE_UINT32(AT91_PIO+AT91_PIO_CODR, 0x06); // DATA+CLOCK LEDs off
for (to = 0; to < 0x200000; to++) ;
for (i = 0; i < 8; i++) {
HAL_WRITE_UINT32(AT91_PIO+AT91_PIO_SODR, ((val>>(7-i)) & 0x01)<<2); // DATA LED
HAL_WRITE_UINT32(AT91_PIO+AT91_PIO_SODR, 0x02); // CLOCK LED on
for (to = 0; to < 0x80000; to++) ;
HAL_WRITE_UINT32(AT91_PIO+AT91_PIO_CODR, 0x02); // CLOCK LED off
for (to = 0; to < 0x40000; to++) ;
HAL_WRITE_UINT32(AT91_PIO+AT91_PIO_CODR, 0x04); // DATA LED off
}
}
void
set_leds(int val)
{
HAL_WRITE_UINT32(AT91_PIO+AT91_PIO_CODR, 0x16);
HAL_WRITE_UINT32(AT91_PIO+AT91_PIO_SODR, val);
}
// End Antenna2k4 changes
/* Use the watchdog to generate a reset */
void hal_at91_reset_cpu(void)
{
HAL_WRITE_UINT32(AT91_WD + AT91_WD_OMR, AT91_WD_OMR_OKEY);
HAL_WRITE_UINT32(AT91_WD + AT91_WD_CMR, AT91_WD_CMR_CKEY);
HAL_WRITE_UINT32(AT91_WD + AT91_WD_CR, AT91_WD_CR_RSTKEY);
HAL_WRITE_UINT32(AT91_WD + AT91_WD_OMR, AT91_WD_OMR_OKEY | AT91_WD_OMR_RSTEN | AT91_WD_OMR_WDEN);
while(1) CYG_EMPTY_STATEMENT;
}
//--------------------------------------------------------------------------
// EOF at91_misc.c
#ifndef CYGONCE_HAL_PLF_IO_H
#define CYGONCE_HAL_PLF_IO_H
//=============================================================================
//
// plf_io.h
//
// EB40A board specific registers
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): tkoeller
// Contributors: tdrury, jjung, jbork
// Date: 2002-06-22
// Purpose: Atmel EB40A board specific registers
// Description:
// Modification: Modified according to Sensitron example to fit current CVS
// version. All changes are shown inside // Begin/End Antenna2k4 changes
// Usage: #include <cyg/hal/plf_io.h>
//
//####DESCRIPTIONEND####
//
//=============================================================================
// these io pins are for the LEDs.
#define EB40A_LED1 0x00000008
#define EB40A_LED2 0x00000010
#define EB40A_LED3 0x00000020
#define EB40A_LED4 0x00000040
// these PIOs double as TCLK1, TIOA1, TIOB1, TCLK2 respectively.
#define EB40A_LED5 0x00010000
#define EB40A_LED6 0x00020000
#define EB40A_LED7 0x00040000
#define EB40A_LED8 0x00080000
#define EB40A_LED_ALL 0x00f00078
// Push buttons. Note that these are connected to interrupt lines.
#define EB40A_SW1 0x00001000
#define EB40A_SW2 0x00000100
#define EB40A_SW3 0x00000002
#define EB40A_SW4 0x00000004
// Push buttons. Note that these are connected to interrupt lines.
#define EB40A_SW1 0x00001000
#define EB40A_SW2 0x00000100
#define EB40A_SW3 0x00000002
#define EB40A_SW4 0x00000004
// Begin Antenna2k4 changes
#define AT91_PS_PCER_PIO 0x100 // Parallel I/O clock
#define AT91_PS_PCER_TC2 0x040 // Timer Counter 2 clock
#define AT91_PS_PCER_TC1 0x020 // Timer Counter 1 clock
#define AT91_PS_PCER_TC0 0x010 // Timer Counter 0 clock
#define AT91_PS_PCER_US1 0x008 // USART 1 clock
#define AT91_PS_PCER_US0 0x004 // USART 0 clock
// Waveform mode definitions
#define AT91_TC_CMRWF_CLKS 0
#define AT91_TC_CMRWF_CLKS_MCK2 (0<<0)
#define AT91_TC_CMRWF_CLKS_MCK8 (1<<0)
#define AT91_TC_CMRWF_CLKS_MCK32 (2<<0)
#define AT91_TC_CMRWF_CLKS_MCK128 (3<<0)
#define AT91_TC_CMRWF_CLKS_MCK1024 (4<<0)
#define AT91_TC_CMRWF_CLKS_XC0 (5<<0)
#define AT91_TC_CMRWF_CLKS_XC1 (6<<0)
#define AT91_TC_CMRWF_CLKS_XC2 (7<<0)
#define AT91_TC_CMRWF_CLKI (1<<3)
#define AT91_TC_CMFWF_BURST_NONE (0<<4)
#define AT91_TC_CMFWF_BURST_XC0 (1<<4)
#define AT91_TC_CMFWF_BURST_XC1 (2<<4)
#define AT91_TC_CMFWF_BURST_XC2 (3<<4)
#define AT91_TC_CMRWF_CPCSTOP (1<<6)
#define AT91_TC_CMRWF_CPCDIS (1<<7)
#define AT91_TC_CMRWF_EEVTEDG_NONE (0<<8)
#define AT91_TC_CMRWF_EEVTEDG_RISE (1<<8)
#define AT91_TC_CMRWF_EEVTEDG_FALL (2<<8)
#define AT91_TC_CMRWF_EEVTEDG_BOTH (3<<8)
#define AT91_TC_CMRWF_EEVT_TIOB (0<<10)
#define AT91_TC_CMRWF_EEVT_XC0 (1<<10)
#define AT91_TC_CMRWF_EEVT_XC1 (2<<10)
#define AT91_TC_CMRWF_EEVT_XC2 (3<<10)
#define AT91_TC_CMRWF_ENETRG (1<<12)
#define AT91_TC_CMRWF_CPCTRG (1<<14)
#define AT91_TC_CMRWF_WAVE (1<<15)
#define AT91_TC_CMRWF_ACPA_NONE (0<<16)
#define AT91_TC_CMRWF_ACPA_SET (1<<16)
#define AT91_TC_CMRWF_ACPA_CLEAR (2<<16)
#define AT91_TC_CMRWF_ACPA_TOGGLE (3<<16)
#define AT91_TC_CMRWF_ACPC_NONE (0<<18)
#define AT91_TC_CMRWF_ACPC_SET (1<<18)
#define AT91_TC_CMRWF_ACPC_CLEAR (2<<18)
#define AT91_TC_CMRWF_ACPC_TOGGLE (3<<18)
#define AT91_TC_CMRWF_AEEVT_NONE (0<<20)
#define AT91_TC_CMRWF_AEEVT_SET (1<<20)
#define AT91_TC_CMRWF_AEEVT_CLEAR (2<<20)
#define AT91_TC_CMRWF_AEEVT_TOGGLE (3<<20)
#define AT91_TC_CMRWF_ASWTRG_NONE (0<<20)
#define AT91_TC_CMRWF_ASWTRG_SET (1<<20)
#define AT91_TC_CMRWF_ASWTRG_CLEAR (2<<20)
#define AT91_TC_CMRWF_ASWTRG_TOGGLE (3<<20)
#define AT91_TC_CMRWF_BCPB_NONE (0<<24)
#define AT91_TC_CMRWF_BCPB_SET (1<<24)
#define AT91_TC_CMRWF_BCPB_CLEAR (2<<24)
#define AT91_TC_CMRWF_BCPB_TOGGLE (3<<24)
#define AT91_TC_CMRWF_BCPC_NONE (0<<26)
#define AT91_TC_CMRWF_BCPC_SET (1<<26)
#define AT91_TC_CMRWF_BCPC_CLEAR (2<<26)
#define AT91_TC_CMRWF_BCPC_TOGGLE (3<<26)
#define AT91_TC_CMRWF_BEEVT_NONE (0<<28)
#define AT91_TC_CMRWF_BEEVT_SET (1<<28)
#define AT91_TC_CMRWF_BEEVT_CLEAR (2<<28)
#define AT91_TC_CMRWF_BEEVT_TOGGLE (3<<28)
#define AT91_TC_CMRWF_BSWTRG_NONE (0<<30)
#define AT91_TC_CMRWF_BSWTRG_SET (1<<30)
#define AT91_TC_CMRWF_BSWTRG_CLEAR (2<<30)
#define AT91_TC_CMRWF_BSWTRG_TOGGLE (3<<30)
// End Antenna2k4 changes
//-----------------------------------------------------------------------------
// end of plf_io.h
#endif // CYGONCE_HAL_PLF_IO_H
--
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