[ECOS] Question on wigglers, debugging Redboot in flash for the XScale target in single step mode

["Krishna Ganugapati" <krishnag at marakicorp dot com>]

Hello,

I'm looking for some clarification on the following issues.

Target;: Custom IXP425 XScale (almost identical to the IXDP development
board, minus the highspeed UART and minus the LEDs), Redboot in ROM mode.
Debugging interface:  Macraigor Wiggler, OCD Commander for the software
debugger on the host.

Situation:  I can successfully download my redboot rom image to Flash using
the Wiggler and the Macraigor Flash Programmer.
When I reset my target, I connect to the JTAG port using the OCD Commander
debugger and attempt to single step through instructions.

Results

1) Through the OCD Debugger, I note that Flash memory is correctly relocated
at 0x000000000.
2) Using the OCD Debugger, I can manual configure the SDRAM registers and
determine that my SDRAM acc ANy recess is good. I flip the
EXP_BUS_CONFIGURATION bits that switc SDRAM and Flash around and determine
that SDRAM is now located at 0x00000000 - I can successfully read and write
words to the first 256 MB so I am assuming memory is good.

3) Reset the board, board is now in bootup mode, flash is at 0x00000000. I
now attempt to single step through my redboot rom image. On the first
instruction, the board transfers control to the reset handler.

Questions:

 a) Has anyone seen behavior like this?
b) On the web it looks like quite a few people have seen something like
this, but there have been no followups on how to fix this.
c) When I reviewed the XScale documentation, it says that when a debugger
executes a single step instruction, a debug event handler is expected and
that this debug event handler is overloaded at the reset handler. It also
says that the debug event handler code needs to be downloaded to the target
through the JTAG. Questions:
    i) Does the OCD Commander software debugger  interface actually download
a debug event handler? If it does, then my conclusions are wrong and I have
to look elsewhere for why things in single step are not progressing, but if
I'm right, then perhaps I need a more sophisticated debugger for my JTAG
interface (the OCD Commander is free). Any recommendations

Other clarifications:
1) One thing that was not very clear in XScale little endian vs big endian
modes was the opcode fetch modes for the XScale. After investigating, my
understanding is that whether in big endian or in little endian mode,
XScale opcode fetches are always in little endian mode. Which is why when
you build a big endian target for the XScale IXP425 board which generates
the instructions in big endian mode, you need to byte swap the image. Is
this correct?

Thanks for any input.

Krishna


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