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RE: Re: Silly question about ARM thumb


Hi,

It is possible to see some improvement in performance with Thumb mode when the core does not have cache (fetching each instruction off the external memory) & the bus size is 16 bits. Obviously, for Thumb mode each instruction fetch needs a single external memory read, where as ARM mode requires 2 reads.

Personally I have not verified such a setup. I have included performance & code size numbers measured on LPC (ARM7) board (32 bit internal memory).

http://geocities.com/michaelanburaj/downloads/dhry_lpc.gif
http://geocities.com/michaelanburaj/downloads/code_lpc.txt

Cheers,
-Mike.



From: "de_sousa_luis" <de_sousa_luis@netcabo.pt>
To: "Grant Edwards" <grante@visi.com>,<ecos-discuss@sources.redhat.com>
Subject: RE: [ECOS] Re: Silly question about ARM thumb
Date: Tue, 22 Feb 2005 16:10:28 -0000

Hi,
I've been reading the AT91 manual from Atmel, and they claim a
performance increase when using thumb mode, but only if the code
is located on external memory, that have a 16 bit data bus.
For example on the AT91EB55 we have 8KB of internal SRAM (32 bits data bus)
and on hte default configuration 256KB of SRAM (16 bit data bus).
If my code is located on the external SRAM (16 bit data bus), and I'm using
thumb mode should I expect the so claimed speed increase ?
When switching between ARM and Thumb mode some performance penalty might occur or not ?
Can anyone coment on this ?
Thanks in advance.
Best regards


Luís de Sousa
-----Mensagem original-----
De: ecos-discuss-owner@ecos.sourceware.org em nome de Grant Edwards
Enviada: ter 22-02-2005 15:48
Para: Øyvind Harboe
Cc: ecos-discuss@sources.redhat.com
Assunto: [ECOS] Re: Silly question about ARM thumb



On Tue, Feb 22, 2005 at 02:25:58PM +0100, Øyvind Harboe wrote:

> If the code is smaller and faster,

It's not. It's slower.

> why aren't all ARM programs compiled w/ARM thumb?

	> This posting quotes 20% code size decrease and 50% speed increase.
	>
	> http://sourceware.org/ml/ecos-discuss/2002-11/msg00036.html

	I don't think the speed increase is something that is seen in
	the general case.  Perhaps the 20% size decrease allowed the
	entire inner loop to stay resident in cache or something like
	that?

	--
	Grant Edwards
	grante@visi.com

	--
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-- Before posting, please read the FAQ: http://ecos.sourceware.org/fom/ecos and search the list archive: http://ecos.sourceware.org/ml/ecos-discuss




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