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rattler fcc1 PIO usage qusetion
- From: Bill <wbarber at nsgdata dot com>
- To: ecos-discuss at sources dot redhat dot com
- Date: Mon, 07 Mar 2005 20:51:38 -0700
- Subject: [ECOS] rattler fcc1 PIO usage qusetion
I am porting eCos to an MPC8247 system and am using the MPC8250 based
rattler board as a model in several areas. One of those is the ethernet
handler for FCC1.
I need a little clarification concerning the ethernet bit level access
functions in rattler_eth.inl.
It appears to me that PIO Port-B bit 7 (FCC1_PHY_RESET) is the physical
ethernet chip reset line, but bits 2 and 3 of PIO Port-C appear to be
used as software only flags to control the operation of the bit level
access functions. In other words Port-C bits 2 and 3 have no defined
hardware function. Is this analysis correct ?? Also, what is the
specific use of the bit level functions ??
Thanks in advance, Bill Barber
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