//========================================================================== // // packages/devs/serial/arm/omap/current/omap5912_serial.c // // OMAP (16750 based UART) serial driver // //========================================================================== //####ECOSGPLCOPYRIGHTBEGIN#### // ------------------------------------------- // This file is part of eCos, the Embedded Configurable Operating System. // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. // // eCos is free software; you can redistribute it and/or modify it under // the terms of the GNU General Public License as published by the Free // Software Foundation; either version 2 or (at your option) any later version. // // eCos is distributed in the hope that it will be useful, but WITHOUT ANY // WARRANTY; without even the implied warranty of MERCHANTABILITY or // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License // for more details. // // You should have received a copy of the GNU General Public License along // with eCos; if not, write to the Free Software Foundation, Inc., // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. // // As a special exception, if other files instantiate templates or use macros // or inline functions from this file, or you compile this file and link it // with other works to produce a work based on this file, this file does not // by itself cause the resulting work to be covered by the GNU General Public // License. However the source code for this file must still be made available // in accordance with section (3) of the GNU General Public License. // // This exception does not invalidate any other reasons why a work based on // this file might be covered by the GNU General Public License. // // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. // at http://sources.redhat.com/ecos/ecos-license/ // ------------------------------------------- //####ECOSGPLCOPYRIGHTEND#### //========================================================================== //#####DESCRIPTIONBEGIN#### // // Author(s): Tom Chase // Contributors: // Date: 2005-05-16 // Purpose: 16750 OMAP specific serial driver // Description: Based on the generic 16x5x driver, // OMAP specific to its 16750 type // //####DESCRIPTIONEND#### // //========================================================================== #include #include #include #include #include #include #include #include #include #include #ifdef CYGPKG_IO_SERIAL_OMAP5912 #include "omap5912_serial.h" typedef struct omap_serial_info { cyg_addrword_t base; int int_num; cyg_interrupt serial_interrupt; cyg_handle_t serial_interrupt_handle; } omap_serial_info; static bool omap_serial_init(struct cyg_devtab_entry *tab); static bool omap_serial_putc(serial_channel *chan, unsigned char c); static Cyg_ErrNo omap_serial_lookup(struct cyg_devtab_entry **tab, struct cyg_devtab_entry *sub_tab, const char *name); static unsigned char omap_serial_getc(serial_channel *chan); static Cyg_ErrNo omap_serial_set_config(serial_channel *chan, cyg_uint32 key, const void *xbuf, cyg_uint32 *len); static void omap_serial_start_xmit(serial_channel *chan); static void omap_serial_stop_xmit(serial_channel *chan); static cyg_uint32 omap_serial_ISR(cyg_vector_t vector, cyg_addrword_t data); static void omap_serial_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data); static SERIAL_FUNS(omap_serial_funs, omap_serial_putc, omap_serial_getc, omap_serial_set_config, omap_serial_start_xmit, omap_serial_stop_xmit ); // Internal function to actually configure the hardware to desired // baud rate, etc. #ifdef CYGPKG_IO_SERIAL_OMAP5912_SERIAL0 static omap_serial_info omap_serial_info0 = {0xfffb0000, CYGNUM_HAL_INTERRUPT_UART1}; #if CYGNUM_IO_SERIAL_OMAP5912_SERIAL0_BUFSIZE > 0 static unsigned char omap_serial_out_buf0[CYGNUM_IO_SERIAL_OMAP5912_SERIAL0_BUFSIZE]; static unsigned char omap_serial_in_buf0[CYGNUM_IO_SERIAL_OMAP5912_SERIAL0_BUFSIZE]; static SERIAL_CHANNEL_USING_INTERRUPTS(omap_serial_channel0, omap_serial_funs, omap_serial_info0, CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_OMAP5912_SERIAL0_BAUD), CYG_SERIAL_STOP_DEFAULT, CYG_SERIAL_PARITY_DEFAULT, CYG_SERIAL_WORD_LENGTH_DEFAULT, CYG_SERIAL_FLAGS_DEFAULT, &omap_serial_out_buf0[0], sizeof(omap_serial_out_buf0), &omap_serial_in_buf0[0], sizeof(omap_serial_in_buf0) ); #else static SERIAL_CHANNEL(omap_serial_channel0, omap_serial_funs, omap_serial_info0, CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_OMAP5912_SERIAL0_BAUD), CYG_SERIAL_STOP_DEFAULT, CYG_SERIAL_PARITY_DEFAULT, CYG_SERIAL_WORD_LENGTH_DEFAULT, CYG_SERIAL_FLAGS_DEFAULT ); #endif DEVTAB_ENTRY(omap_serial_io0, CYGDAT_IO_SERIAL_OMAP5912_SERIAL0_NAME, 0, // Does not depend on a lower level interface &cyg_io_serial_devio, omap_serial_init, omap_serial_lookup, // Serial driver may need initializing &omap_serial_channel0 ); #endif // CYGPKG_IO_SERIAL_OMAP5912_SERIAL0 #ifdef CYGPKG_IO_SERIAL_OMAP5912_SERIAL1 static omap_serial_info omap_serial_info1 = {0xfffb0800, CYGNUM_HAL_INTERRUPT_UART2}; #if CYGNUM_IO_SERIAL_OMAP5912_SERIAL1_BUFSIZE > 0 static unsigned char omap_serial_out_buf1[CYGNUM_IO_SERIAL_OMAP5912_SERIAL1_BUFSIZE]; static unsigned char omap_serial_in_buf1[CYGNUM_IO_SERIAL_OMAP5912_SERIAL1_BUFSIZE]; static SERIAL_CHANNEL_USING_INTERRUPTS(omap_serial_channel1, omap_serial_funs, omap_serial_info1, CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_OMAP5912_SERIAL1_BAUD), CYG_SERIAL_STOP_DEFAULT, CYG_SERIAL_PARITY_DEFAULT, CYG_SERIAL_WORD_LENGTH_DEFAULT, CYG_SERIAL_FLAGS_DEFAULT, &omap_serial_out_buf1[0], sizeof(omap_serial_out_buf1), &omap_serial_in_buf1[0], sizeof(omap_serial_in_buf1) ); #else static SERIAL_CHANNEL(omap_serial_channel1, omap_serial_funs, omap_serial_info1, CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_OMAP5912_SERIAL1_BAUD), CYG_SERIAL_STOP_DEFAULT, CYG_SERIAL_PARITY_DEFAULT, CYG_SERIAL_WORD_LENGTH_DEFAULT, CYG_SERIAL_FLAGS_DEFAULT ); #endif DEVTAB_ENTRY(omap_serial_io1, CYGDAT_IO_SERIAL_OMAP5912_SERIAL1_NAME, 0, // Does not depend on a lower level interface &cyg_io_serial_devio, omap_serial_init, omap_serial_lookup, // Serial driver may need initializing &omap_serial_channel1 ); #endif // CYGPKG_IO_SERIAL_OMAP5912_SERIAL1 #ifdef CYGPKG_IO_SERIAL_OMAP5912_SERIAL2 static omap_serial_info omap_serial_info2 = {0xfffb9800, CYGNUM_HAL_INTERRUPT_UART3}; #if CYGNUM_IO_SERIAL_OMAP5912_SERIAL2_BUFSIZE > 0 static unsigned char omap_serial_out_buf2[CYGNUM_IO_SERIAL_OMAP5912_SERIAL2_BUFSIZE]; static unsigned char omap_serial_in_buf2[CYGNUM_IO_SERIAL_OMAP5912_SERIAL2_BUFSIZE]; static SERIAL_CHANNEL_USING_INTERRUPTS(omap_serial_channel2, omap_serial_funs, omap_serial_info2, CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_OMAP5912_SERIAL2_BAUD), CYG_SERIAL_STOP_DEFAULT, CYG_SERIAL_PARITY_DEFAULT, CYG_SERIAL_WORD_LENGTH_DEFAULT, CYG_SERIAL_FLAGS_DEFAULT, &omap_serial_out_buf2[0], sizeof(omap_serial_out_buf2), &omap_serial_in_buf2[0], sizeof(omap_serial_in_buf2) ); #else static SERIAL_CHANNEL(omap_serial_channel2, omap_serial_funs, omap_serial_info2, CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_OMAP5912_SERIAL2_BAUD), CYG_SERIAL_STOP_DEFAULT, CYG_SERIAL_PARITY_DEFAULT, CYG_SERIAL_WORD_LENGTH_DEFAULT, CYG_SERIAL_FLAGS_DEFAULT ); #endif DEVTAB_ENTRY(omap_serial_io2, CYGDAT_IO_SERIAL_OMAP5912_SERIAL2_NAME, 0, // Does not depend on a lower level interface &cyg_io_serial_devio, omap_serial_init, omap_serial_lookup, // Serial driver may need initializing &omap_serial_channel2 ); #endif // CYGPKG_IO_SERIAL_OMAP5912_SERIAL2 static bool serial_config_port(serial_channel *chan, cyg_serial_info_t *new_config, bool init) { omap_serial_info *ser_chan = (omap_serial_info *)chan->dev_priv; cyg_addrword_t base = ser_chan->base; unsigned short baud_divisor = select_baud[new_config->baud]; unsigned char _mcr; unsigned char _ier; if (baud_divisor == 0) return false; // Invalid configuration #if 0 // done in omap5912_diag.c already { unsigned short temp; HAL_READ_UINT16(ULPD_SOFT_REQ, temp); if(base == 0xfffb0000){ // makes sure serial0 (UART1) is clocked temp |= BIT_09; } else if(base == 0xfffb0800){ // makes sure serial1 (UART2) is clocked temp |= BIT_10; } else if(base == 0xfffb9800){ // makes sure serial1 (UART2) is clocked temp |= BIT_11; } HAL_WRITE_UINT16(ULPD_SOFT_REQ, temp); } #endif // Disable port interrupts while changing hardware HAL_WRITE_UINT8(base+REG_lcr, 0xbf); // allow access to EFR register HAL_WRITE_UINT8(base+REG_efr, BIT_04);// allow access to mcr,fcr, and ier HAL_WRITE_UINT8(base+REG_lcr, 0x00); // allow access to ier & mcr regs HAL_READ_UINT8(base+REG_ier, _ier); // store interrupt enable register HAL_WRITE_UINT8(base+REG_ier, 0); //disable ints HAL_WRITE_UINT8(base+REG_mdr1, 0x07); // hold uart in reset HAL_WRITE_UINT8(base+REG_scr, 0x00); // reset supp control no dma etc. // make sure _mcr bit 6 is clear HAL_READ_UINT8(base+REG_mcr, _mcr); HAL_WRITE_UINT8(base+REG_mcr,_mcr & ~(BIT_06)); // now set addressing to allow access to divisor HAL_WRITE_UINT8(base+REG_lcr, LCR_DL); HAL_WRITE_UINT8(base+REG_dlh, baud_divisor >> 8); // load divisor HAL_WRITE_UINT8(base+REG_dll, baud_divisor & 0xFF); HAL_WRITE_UINT8(base+REG_lcr, select_word_length[new_config->word_length - CYGNUM_SERIAL_WORD_LENGTH_5] | select_stop_bits[new_config->stop] | select_parity[new_config->parity] ); // store lcr HAL_WRITE_UINT8(base+REG_mdr1, 0x00); // enable uart in 16x mode if (init) { #ifdef CYGPKG_IO_SERIAL_OMAP5912_FIFO unsigned char _fcr_thresh; switch(CYGPKG_IO_SERIAL_OMAP5912_FIFO_RX_THRESHOLD) { default: case 8: _fcr_thresh=FCR_RT8; break; case 16: _fcr_thresh=FCR_RT16; break; case 56: _fcr_thresh=FCR_RT56; break; case 60: _fcr_thresh=FCR_RT60; break; } _fcr_thresh|=FCR_FE|FCR_CRF|FCR_CTF; HAL_WRITE_UINT8(base+REG_fcr, _fcr_thresh); // Enable and clear FIFO #endif if (chan->out_cbuf.len != 0) { _ier = IER_RCV; } else { _ier = 0; } // Master interrupt enable HAL_WRITE_UINT8(base+REG_mcr, MCR_DTR | MCR_RTS); } #ifdef CYGOPT_IO_SERIAL_SUPPORT_LINE_STATUS _ier |= (IER_LS|IER_MS); #endif HAL_WRITE_UINT8(base+REG_ier, _ier); if (new_config != &chan->config) { chan->config = *new_config; } return true; } // Function to initialize the device. Called at bootstrap time. static bool omap_serial_init(struct cyg_devtab_entry *tab) { serial_channel *chan = (serial_channel *)tab->priv; omap_serial_info *ser_chan = (omap_serial_info *)chan->dev_priv; #ifdef CYGDBG_IO_INIT diag_printf("OMAP SERIAL init - dev: %x.%d\n", ser_chan->base, ser_chan->int_num); #endif // Really only required for interrupt driven devices (chan->callbacks->serial_init)(chan); if (chan->out_cbuf.len != 0) { cyg_drv_interrupt_create(ser_chan->int_num, 0, (cyg_addrword_t)chan, omap_serial_ISR, omap_serial_DSR, &ser_chan->serial_interrupt_handle, &ser_chan->serial_interrupt); cyg_drv_interrupt_configure(ser_chan->int_num, 1, /* level triggered */ 1); /* high level */ cyg_drv_interrupt_attach(ser_chan->serial_interrupt_handle); cyg_drv_interrupt_unmask(ser_chan->int_num); } serial_config_port(chan, &chan->config, true); return true; } // This routine is called when the device is "looked" up (i.e. attached) static Cyg_ErrNo omap_serial_lookup(struct cyg_devtab_entry **tab, struct cyg_devtab_entry *sub_tab, const char *name) { serial_channel *chan = (serial_channel *)(*tab)->priv; // Really only required for interrupt driven devices (chan->callbacks->serial_init)(chan); return(ENOERR); } // Send a character to the device output buffer. // Return 'true' if character is sent to device static bool omap_serial_putc(serial_channel *chan, unsigned char c) { cyg_uint8 _lsr; omap_serial_info *ser_chan = (omap_serial_info *)chan->dev_priv; cyg_addrword_t base = ser_chan->base; HAL_READ_UINT8(base+REG_lsr, _lsr); if (_lsr & LSR_THE) { // Transmit buffer is empty HAL_WRITE_UINT8(base+REG_thr, c); return(true); } // No space return(false); } // Fetch a character from the device input buffer, waiting if necessary static unsigned char omap_serial_getc(serial_channel *chan) { unsigned char c; cyg_uint8 _lsr; omap_serial_info *ser_chan = (omap_serial_info *)chan->dev_priv; cyg_addrword_t base = ser_chan->base; // Wait for char do { HAL_READ_UINT8(base+REG_lsr, _lsr); } while ((_lsr & LSR_RSR) == 0); HAL_READ_UINT8(base+REG_rhr, c); return(c); } // Set up the device characteristics; baud rate, etc. static Cyg_ErrNo omap_serial_set_config(serial_channel *chan, cyg_uint32 key, const void *xbuf, cyg_uint32 *len) { switch (key) { case CYG_IO_SET_CONFIG_SERIAL_INFO: { cyg_serial_info_t *config = (cyg_serial_info_t *)xbuf; if ( *len < sizeof(cyg_serial_info_t) ) { return -EINVAL; } *len = sizeof(cyg_serial_info_t); if ( true != serial_config_port(chan, config, false) ) return -EINVAL; } break; #ifdef CYGOPT_IO_SERIAL_FLOW_CONTROL_HW case CYG_IO_SET_CONFIG_SERIAL_HW_RX_FLOW_THROTTLE: { cyg_uint8 _mcr; omap_serial_info *ser_chan = (omap_serial_info *)chan->dev_priv; cyg_addrword_t base = ser_chan->base; cyg_uint32 *f = (cyg_uint32 *)xbuf; unsigned char mask=0; if ( *len < sizeof(*f) ) return -EINVAL; if ( chan->config.flags & CYGNUM_SERIAL_FLOW_RTSCTS_RX ) mask = MCR_RTS; if ( chan->config.flags & CYGNUM_SERIAL_FLOW_DSRDTR_RX ) mask |= MCR_DTR; HAL_READ_UINT8(base+REG_mcr, _mcr); if (*f) // we should throttle _mcr &= ~mask; else // we should no longer throttle _mcr |= mask; HAL_WRITE_UINT8(base+REG_mcr, _mcr); } break; case CYG_IO_SET_CONFIG_SERIAL_HW_FLOW_CONFIG: // Nothing to do because we do support both RTSCTS and DSRDTR flow // control. // Other targets would clear any unsupported flags here. // We just return ENOERR. break; #endif default: return( -EINVAL); } return(ENOERR); } // Enable the transmitter on the device static void omap_serial_start_xmit(serial_channel *chan) { omap_serial_info *ser_chan = (omap_serial_info *)chan->dev_priv; cyg_addrword_t base = ser_chan->base; cyg_uint8 _ier; HAL_READ_UINT8(base+REG_ier, _ier); _ier |= IER_XMT; // Enable xmit interrupt HAL_WRITE_UINT8(base+REG_ier, _ier); } // Disable the transmitter on the device static void omap_serial_stop_xmit(serial_channel *chan) { omap_serial_info *ser_chan = (omap_serial_info *)chan->dev_priv; cyg_addrword_t base = ser_chan->base; cyg_uint8 _ier; HAL_READ_UINT8(base+REG_ier, _ier); _ier &= ~IER_XMT; // Disable xmit interrupt HAL_WRITE_UINT8(base+REG_ier, _ier); } // Serial I/O - low level interrupt handler (ISR) static cyg_uint32 omap_serial_ISR(cyg_vector_t vector, cyg_addrword_t data) { serial_channel *chan = (serial_channel *)data; omap_serial_info *ser_chan = (omap_serial_info *)chan->dev_priv; cyg_drv_interrupt_mask(ser_chan->int_num); cyg_drv_interrupt_acknowledge(ser_chan->int_num); return(CYG_ISR_CALL_DSR); // Cause DSR to be run } // Serial I/O - high level interrupt handler (DSR) static void omap_serial_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) { serial_channel *chan = (serial_channel *)data; omap_serial_info *ser_chan = (omap_serial_info *)chan->dev_priv; cyg_addrword_t base = ser_chan->base; cyg_uint8 _iir; // Check if we have an interrupt pending - note that the interrupt // is pending of the low bit of the iir is *0*, not 1. HAL_READ_UINT8(base+REG_iir, _iir); while ((_iir & IIR_nIP) == 0) { switch (_iir&0xE) { case IIR_Rx: case IIR_RxTO: { cyg_uint8 _lsr; unsigned char c; HAL_READ_UINT8(base+REG_lsr, _lsr); while(_lsr & LSR_RSR) { HAL_READ_UINT8(base+REG_rhr, c); (chan->callbacks->rcv_char)(chan, c); HAL_READ_UINT8(base+REG_lsr, _lsr); } break; } case IIR_Tx: (chan->callbacks->xmt_char)(chan); break; #ifdef CYGOPT_IO_SERIAL_SUPPORT_LINE_STATUS case IIR_LS: { cyg_serial_line_status_t stat; cyg_uint8 _lsr, _rhr; HAL_READ_UINT8(base+REG_lsr, _lsr); /* Read (and discard) a character so we can clear * the error forcing the line status interrupt. * Note that this means that characters will be lost * in the presence of line errors. * This could be fixed someday. */ HAL_READ_UINT8(base+REG_rhr, _rhr); // this might look expensive, but it is rarely the case that // more than one of these is set stat.value = 1; if ( _lsr & LSR_OE ) { stat.which = CYGNUM_SERIAL_STATUS_OVERRUNERR; (chan->callbacks->indicate_status)(chan, &stat ); } if ( _lsr & LSR_PE ) { stat.which = CYGNUM_SERIAL_STATUS_PARITYERR; (chan->callbacks->indicate_status)(chan, &stat ); } if ( _lsr & LSR_FE ) { stat.which = CYGNUM_SERIAL_STATUS_FRAMEERR; (chan->callbacks->indicate_status)(chan, &stat ); } if ( _lsr & LSR_BI ) { stat.which = CYGNUM_SERIAL_STATUS_BREAK; (chan->callbacks->indicate_status)(chan, &stat ); } } break; case IIR_MS: { cyg_serial_line_status_t stat; cyg_uint8 _msr; HAL_READ_UINT8(base+REG_msr, _msr); #ifdef CYGOPT_IO_SERIAL_FLOW_CONTROL_HW if ( _msr & MSR_DDSR ) if ( chan->config.flags & CYGNUM_SERIAL_FLOW_DSRDTR_TX ) { stat.which = CYGNUM_SERIAL_STATUS_FLOW; stat.value = (0 != (_msr & MSR_DSR)); (chan->callbacks->indicate_status)(chan, &stat ); } if ( _msr & MSR_DCTS ) if ( chan->config.flags & CYGNUM_SERIAL_FLOW_RTSCTS_TX ) { stat.which = CYGNUM_SERIAL_STATUS_FLOW; stat.value = (0 != (_msr & MSR_CTS)); (chan->callbacks->indicate_status)(chan, &stat ); } #endif } break; #endif default: // Yes, this assertion may well not be visible. *But* // if debugging, we may still successfully hit a breakpoint // on cyg_assert_fail, which _is_ useful CYG_FAIL("unhandled serial interrupt state"); } HAL_READ_UINT8(base+REG_iir, _iir); } // while cyg_drv_interrupt_unmask(ser_chan->int_num); } #endif // EOF omap5912_serial.c