[ECOS] J3 flash lockbits across reset

[alfred hitch <alfred dot hitch at gmail dot com>]

Hi,

I am confused on what is the correct behavior across power resets
(of hardware) for J3 flash'es.

1) Will all sectors which were locked before power reset, remain so ?

I am confused by some posts on net, saying they get locked (all) by
default across resets (irr. of before power reset status)

Some say, it is unlocked (all blocks )by default  across resets.

I dont think flash should change status across resets. It should
preserve whatever I locked before reboot and vice versa.

2) Is it dependant on version, looking at j3 v d there seem to be a
bug on registers for same also which was fixed. Gives me an errie
feeling that responses on net were diff. because of people using diff.
kernels and flash revisions and so diff. observations ?

3) Intel FAQ says, that :

While setting up a Set Block Lock-Bit or Clear Block-Bits operation.
must the first and second bus cycles be sequential write operations
(i.e., no other bus operations to the flash between write cycles)?
For the Set and Clear Block Lock Bit operations, the first and second
bus cycles must be sequential. If the 28xxxJ3 receives any other
command during the second write cycle, an invalid command sequence
occurs. This causes the mode (the first bus cycle) to be aborted, and
bits 5 and 4 in the Status Register will be set.

So, will this effectively mean that I cannot use this lock / unlock
feature unless I can be sure there will be no read / write etc from
ANY flash location ? as this will break the WSM sequence ?

Sorry I am trying to design a feature (and dont have hardware to play
with) so looking to be sure.

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