RE: [ECOS] Re: DSR Scheduling Problem

["Paul D. DeRocco" <pderocco at ix dot netcom dot com>]

> From: Grant Edwards
>
> I still maintain that your application is either broken or you
> don't have enough CPU.  If one interrupts source requires so
> much DSR time that others can't run, then there is simply
> something wrong.  You seem to prefer a tx underrun error to an
> rx overrun error.  I guarantee you're going to get one or the
> other.  On the systems I work on, either is equally fatal, so
> it is not the case that FIFO is better than LIFO.  Both work
> equally well.

If the transmitter has a hardware FIFO, and the software transmits one byte
per interrupt, then presenting a block of data to it after an idle period
will invoke the ISR/DSR a slew of times until the FIFO is full. This will
happen even if the average interrupt rate is eventually throttled to a
reasonable value by the serial transmission rate, once the FIFO is full. I
don't know if that accounts for the 38ms in this person's situation, but if
the FIFO is large it could certainly tie things up for a significant amount
of time.

--

Ciao,               Paul D. DeRocco
Paul                mailto:pderocco@ix.netcom.com


-- 
Before posting, please read the FAQ: http://ecos.sourceware.org/fom/ecos
and search the list archive: http://ecos.sourceware.org/ml/ecos-discuss