[ECOS] Re: DSR Scheduling Problem

[Grant Edwards <grante at visi dot com>]

On 2006-01-14, Paul D. DeRocco <pderocco@ix.netcom.com> wrote:

>> I still maintain that your application is either broken or you
>> don't have enough CPU.  If one interrupts source requires so
>> much DSR time that others can't run, then there is simply
>> something wrong.  You seem to prefer a tx underrun error to an
>> rx overrun error.  I guarantee you're going to get one or the
>> other.  On the systems I work on, either is equally fatal, so
>> it is not the case that FIFO is better than LIFO.  Both work
>> equally well.
>
> If the transmitter has a hardware FIFO, and the software
> transmits one byte per interrupt,

Then the sofware is completely and utterly broken.  It doesn't
deserve to work.

> then presenting a block of data to it after an idle period
> will invoke the ISR/DSR a slew of times until the FIFO is
> full.

That's insane.  Nobody with a clue would write software like
that.  When you get a TX interrupt you write data to the tx
FIFO until it's full.

> This will happen even if the average interrupt rate is
> eventually throttled to a reasonable value by the serial
> transmission rate, once the FIFO is full. I don't know if that
> accounts for the 38ms in this person's situation, but if the
> FIFO is large it could certainly tie things up for a
> significant amount of time.

You're describing completely broken software.  It needs to be
fixed.

-- 
Grant Edwards                   grante             Yow!  That's a decision
                                  at               that can only be made
                               visi.com            between you & SY SPERLING!!


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