[ECOS] Re: Make better use of the 16x5x UART transmit FIFO

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Daniel!

Thanks for the recent patch for generic 16x5x UARTs.

I'm doing something very similar except that I allow tx_fifo_threshold
to be set via CDL and I alter tx_fifo_available to be tx_fifo_size -
tx_fifo_threshold. This causes the UART to interrupt at the threshold
instead of when the TX FIFO is completely empty. It helps avoids gaps in
the transmit stream at high bit rates.

Now to my question for you and any UART experts...

I think I see a problem with the generic 16x5x code. In pc_serial_DSR()
during the handling of receive-data-available, the code repeated reads
the line-status register but doesn't look at (or act on) any of the
line-status error bits.

Doesn't just reading the line-status register causes the error bits and
the line-status interrupt to clear? Doesn't it seem like receive errors
would only be caught (and the call-backs executed) in the first byte in
the RX FIFO?



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