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cache configuration for 946es
- From: "Sinan KAYA" <sinan dot kaya at siemens dot com>
- To: <ecos-discuss at ecos dot sourceware dot org>
- Date: Tue, 5 Dec 2006 15:45:01 +0200
- Subject: [ECOS] cache configuration for 946es
Hi again,
Ä checked the values from cache type register of arm
Ät says
icache_Asc =2 -> four way associative
Äcache_Sz = 4 ->8kb
Äcache_pl = 2 -> 8 words per line
dcache_Asc =2 -> four way associative
dcache_Sz = 3 ->4kb
dcache_pl = 2 -> 8 words per line
# define HAL_ICACHE_SIZE 0x2000
# define HAL_ICACHE_LINE_SIZE 32
# define HAL_ICACHE_WAYS 4
# define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
# define HAL_DCACHE_SIZE 0x1000
# define HAL_DCACHE_LINE_SIZE 32
# define HAL_DCACHE_WAYS 4
# define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
How is the relationship between HAL_ICACHE_LINE_SIZE and 8 words per line. Is the unit of HAL_ICACHE_LINE_SIZE bytes ?
Sinan.
-----Original Message-----
From: Yin Wen Chao (åæè) [mailto:yinwenchao@vimicro.com]
Sent: Tuesday, December 05, 2006 11:12 AM
To: Sinan KAYA
Subject: Re: [ECOS] cache configuration for 946es
Hi,Sinan KAYA
You should compare those cache information from the document you mentioned
with those from the ARM you have.
Reference:
http://www.arm.com/pdfs/DDI0155A_946ES.pdf
You can access the cache type register by reading CP15 register c0 with the Opcode_2
field set to 1. For example:
MRC p15, 0, <Rd>, c0, c0, 1; returns cache details
-----------------------------------
>Hi,
>i have a 946es variant and i'm unable to pass kcache2 test even though
>other cache tests, cache and kcache1 pass.
>
>I googled a little bit. Previous posts say that this test is designed to
>find misconfigurations. So, i assume i have a misconfiguration. The
>document of board tells me that i have 8 kb instruction cache, 4kb data
>cache with four way associative set and 1024 byte segments.
>
>Each segment consists of 32 lines with 32 ( 8 x 4 bytes) bytes.
>
>and here is my configuration
>
>#elif defined(CYGPKG_HAL_ARM_ARM9_ARM946ES)
>
># define HAL_ICACHE_SIZE 0x2000
># define HAL_ICACHE_LINE_SIZE 32
># define HAL_ICACHE_WAYS 4
># define HAL_ICACHE_SETS
>(HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
>
># define HAL_DCACHE_SIZE 0x1000
># define HAL_DCACHE_LINE_SIZE 32
># define HAL_DCACHE_WAYS 4
># define HAL_DCACHE_SETS
>(HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
>
># define HAL_WRITE_BUFFER 32
># define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX
># define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_STEP 0x20
># define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_LIMIT 0x400
>
>
>can anybody see a mistake?
>
>--
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>and search the list archive: http://ecos.sourceware.org/ml/ecos-discuss
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