Re: [ECOS] Re: PowerPC FEC doesn't ping

["Tales Toledo" <toledo dot tales at gmail dot com>]

On 7/28/07, Gary Thomas <gary@mlbassoc.com> wrote:
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> Tales Toledo wrote:
> > On 7/27/07, Tales Toledo <toledo.tales@gmail.com> wrote:
> >> Hi,
> >>
> >> is there some additional special cdl_option for FEC?
> >>
> >> I can get ** FEC Info: PHY LINK already UP \n message from redboot
> >> boot, configure ip_addresses, but I can get a reply from host or even
> >> reply its requests because FEC can't send packages (I have checked
> >> with wireshark).
> >
> > I also check TXD0 close to phy with an oscilloscope and seems that
> > PowerPC FEC (hw is fine because it works with another sw) doesn't
> > transmit any package.
> >
> > I can see the debug messages at redboot console
> >
> > RedBoot> ping -h 192.168.1.100
> > Ethernet send:
> > 0000545C: FF FF FF FF FF FF 7C 71  43 A6 7C 92 08 06        |......|qC.|...  |
> > Ethernet send:
> > 0000545C: FF FF FF FF FF FF 7C 71  43 A6 7C 92 08 06        |......|qC.|...  |
> > Ethernet send:
> > 0000545C: FF FF FF FF FF FF 7C 71  43 A6 7C 92 08 06        |......|qC.|...  |
> >
> > Is there some low level debug for FEC driver to address this issue?
>
> Check your I/O port configuration - this is different
> for every processor (852 vs 87x vs ...).  If it's not
> right, the FEC will not be connected to the outside
> world!

You're right. I'm using MPC880 and FEC pins are spread over all ports.
At this moment I can't contribute with a patch because I'm working in
a proprietary hardware. I will try to get Adder885 board and ask them
if we can add their eCos port to cvs and I can also add any changes I
made.

Anyway, just for close this subject and register here in other to help
others, here is a brief description of changes:

@ppc8xx.h

Add description for port E
   /* Port E */
    volatile unsigned long	pio_pedir;	/* port e data direction reg */
    volatile unsigned long	pio_pepar;	/* port e pin assignment reg */
    volatile unsigned long	pio_peso;	/* port e special options reg */
    volatile unsigned long	pio_peodr;	/* port e open drain reg */
    volatile unsigned long	pio_pedat;	/* port e data reg */

    /* CP Timing Register */
    volatile unsigned long	cp_cptr;	/* RMII timing register */

@ if_fec.h

Add port configuration

#if defined (CYGHWR_HAL_POWERPC_MPC8XX_880)
    // MII1: TXD0, TXER, TXD1, RXER, RXDV, RXD0, RXD1
    eppc->pio_papar |= 0xF830;
    eppc->pio_padir &= ~0xF000;
    eppc->pio_padir |= 0x0830;
    // MII1: TXCLK, RXD3
    eppc->pip_pbpar |= 0x00001001;
    eppc->pip_pbdir &= ~0x00001001;
    // MII1: TXD3, TXD2
    eppc->pio_pcpar |= 0x000C;
    eppc->pio_pcdir &= ~0x000C;
    // MII1: MDC
    eppc->pio_pdpar |= 0x0080;
    eppc->pio_pddir &= ~0x0080;
    // MII1: RXCLK, RXD2
    eppc->pio_pepar |= 0x00000003;
    eppc->pio_pedir |= 0x00000003;
    eppc->pio_peso  &= ~0x00000003;
#else
    eppc->pio_pdpar = 0x1FFF;
    CYGARC_MFSPR( CYGARC_REG_PVR, proc_rev );
#define PROC_REVB 0x0020
    if ((proc_rev & 0x0000FFFF) == PROC_REVB) {
        eppc->pio_pddir = 0x1C58;
    } else {
        eppc->pio_pddir = 0x1FFF;
    }
#endif // CYGHWR_HAL_POWERPC_MPC8XX_880

Thx,
TT.

>
> - --
> - ------------------------------------------------------------
> Gary Thomas                 |  Consulting for the
> MLB Associates              |    Embedded world
> - ------------------------------------------------------------
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