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Cortex M3 architecture


Hello everyone

I'm planning on starting an initial effort to port eCos to the Cortex M3 architecture, using the STM3210E-EVAL board as the initial target. After studying the current ARM architecture code, as well as some of it's variants and platforms, I wonder if the Cortex M3 should be implemented as a variant of the ARM architecture, or as a complete new architecture of it's own. I think I'd prefer to start a new architecture, as the M3 differs quite a bit from the normal ARM architecture in terms of context switching as well as interrupt and exception handing. Also the M3 exclusively runs Thumb2 instructions, so all the current assembler code using normal ARM instructions cannot be used. I think writing a new architecture saves us from introducing quite a mess in the current ARM architecture code. What do you think?

I wonder if the other Cortex variants (A8, A9, R4, M1) should be considered for porting from the beginning. My focus is clearly on the M3, but if anyone is willing to work on the other variants this should be considered now.

Also if anyone is interested to help, please inform me.

Best regards,
Simon

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