[ECOS] Interrupt mode for MIPS32 in eCos - compatibility or vectored

[Elad Yosef <elad dot yosef at gmail dot com>]

Hi,
My MIPS32 4KEc supports Interrupt Vectors or compatibility mode.
>From what is see in the eCos code is only support the compatibility mode
So that SW decodes the cause register and jumps to handler according
to the vsr_table.

Interrupt Vectors is functionality in the MIPS32.
When it is on, the CPU HW decodes the cause register to get the
exception/interrupt number.
And then it jumps to the handler.
The handlers are in a fixed location that is calculated by formula
that looks like  - BASE+(exp_code*space_between_handlers)
the spacing is configurable in the MIPS.
It is up to the SW to supply the handlers and place then in the
correct location. The handlers are basically the ISR

My questions are:
-Am I wrong in my assumption ?
-Can eCos supports Interrupt Vectors, so decode of the cause and the
jump to handler are done by HW ?


Thanks
Elad

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