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Interrupt handling under eCOS for the arm AT91SAM7s
- From: Bob Brusa <bob dot brusa at gmail dot com>
- To: discuss ecos <ecos-discuss at ecos dot sourceware dot org>
- Date: Wed, 22 Aug 2012 09:27:23 +0200
- Subject: [ECOS] Interrupt handling under eCOS for the arm AT91SAM7s
Hi,
I use an ISR that has considerable work to. Clearly, a job for a dsr,
but I found, that using a dsr is too time consuming, so I must do
everything in the isr (A screenshot of the ISR is available here:
https://dl.dropbox.com/u/13412634/Screenshot%20-%2021.08.jpg)
The ISR handles 4 pwm channels - all producing interrupts at a rate of 1
ms. 3 of the channels run syncronously and hence only one of them has
interrupts enabled. The 4th channels also triggers interrupts every ms,
but is not in phase with the other 3 channels. The pwm interrupts have
lowest priority of all interrupts in my system.
Upon entry in the pwm_isr, I clear flags, mask the interrupt of the
pwm-hardware on the level of the interrupt controller (AIC) and enable
interrupts again. This should allow higher priority interrupts to come
through, but no pwm interrupts while the pwm_isr is busy. This according
to my understanding. But it is obviously wrong, because the primitve
"semaphore" I implemented tells me, that a 2nd pwm interrupt interrupts
the first one.
One explanation I have for this is, that one of the higher priority
interrupts clears the interrupt mask of the pwm channels - which I would
consider a bug of eCos.
Onother explanation could be, that the system timer interrupts the
pwm_isr and runs a task and of course, many threads in my system access
globals of the pwm_isr, doing this within
mask-pwm-interrupts/unmask-pwm-interrupts brackets. But it would
surprise me that ecos runs a thread while an isr is still unfinished.
Any comments?
Bob
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