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PowerPC - Improve cache control


Index: hal/common/current/ChangeLog
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/common/current/ChangeLog,v
retrieving revision 1.80
diff -u -5 -p -r1.80 ChangeLog
--- hal/common/current/ChangeLog	11 Sep 2002 12:14:51 -0000	1.80
+++ hal/common/current/ChangeLog	13 Nov 2002 21:01:21 -0000
@@ -1,5 +1,9 @@
+2002-11-13  Gary Thomas  <gthomas@ecoscentric.com>
+
+	* cdl/hal.cdl: Add CDL control over DATA cache startup mode.
+
 2002-09-11  Mark Salter  <msalter@redhat.com>
 
 	* include/hal_if.h: Add __COMMCTL_ENABLE_LINE_FLUSH and
 	__COMMCTL_DISABLE_LINE_FLUSH.
 
Index: hal/common/current/cdl/hal.cdl
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/common/current/cdl/hal.cdl,v
retrieving revision 1.16
diff -u -5 -p -r1.16 hal.cdl
--- hal/common/current/cdl/hal.cdl	23 May 2002 23:02:46 -0000	1.16
+++ hal/common/current/cdl/hal.cdl	13 Nov 2002 21:01:22 -0000
@@ -7,10 +7,11 @@
 # ====================================================================
 #####ECOSGPLCOPYRIGHTBEGIN####
 ## -------------------------------------------
 ## This file is part of eCos, the Embedded Configurable Operating System.
 ## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+## Copyright (C) 2002 Gary Thomas
 ##
 ## eCos is free software; you can redistribute it and/or modify it under
 ## the terms of the GNU General Public License as published by the Free
 ## Software Foundation; either version 2 or (at your option) any later version.
 ##
@@ -126,19 +127,28 @@ cdl_package CYGPKG_HAL {
         no_define
         description   "
             These options let the default behaviour of the caches 
             be easily configurable."
 
-        cdl_option CYGSEM_HAL_ENABLE_DCACHE_ON_STARTUP {
+        cdl_component CYGSEM_HAL_ENABLE_DCACHE_ON_STARTUP {
             display       "Enable DATA cache on startup"
             default_value 1
             description   "
                 Enabling this option will cause the data cache to be enabled
                 as soon as practicable when eCos starts up.  One would choose
                 to disable this if the data cache cannot safely be turned on,
                 such as a case where the cache(s) require additional platform
                 specific setup."
+            cdl_option CYGSEM_HAL_DCACHE_STARTUP_MODE {
+                display       "DATA cache mode on startup"
+                flavor        data
+                legal_values  { "COPYBACK" "WRITETHRU" }
+                default_value { "COPYBACK" }
+                description   "
+                    This option controls the mode the cache will be set to
+                when enabled on startup."
+            }
         }
 
         cdl_option CYGSEM_HAL_ENABLE_ICACHE_ON_STARTUP {
             display       "Enable INSTRUCTION cache on startup"
             default_value 1
Index: hal/powerpc/arch/current/ChangeLog
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/arch/current/ChangeLog,v
retrieving revision 1.43
diff -u -5 -p -r1.43 ChangeLog
--- hal/powerpc/arch/current/ChangeLog	5 Aug 2002 12:49:46 -0000	1.43
+++ hal/powerpc/arch/current/ChangeLog	13 Nov 2002 21:01:37 -0000
@@ -1,5 +1,10 @@
+2002-11-13  Gary Thomas  <gthomas@ecoscentric.com>
+
+	* src/hal_misc.c (hal_enable_caches): Support new CDL options for
+	how [mode] to enable DATA cache.
+
 2002-08-05  Gary Thomas  <gary@chez-thomas.org>
 2002-08-05  Bob Koninckx <bob.koninckx@mech.kuleuven.ac.be>	
 
 	* include/arch.inc: hal_fpu_load regs was not loading registers!
 
Index: hal/powerpc/arch/current/src/hal_misc.c
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/arch/current/src/hal_misc.c,v
retrieving revision 1.22
diff -u -5 -p -r1.22 hal_misc.c
--- hal/powerpc/arch/current/src/hal_misc.c	23 May 2002 23:04:14 -0000	1.22
+++ hal/powerpc/arch/current/src/hal_misc.c	13 Nov 2002 21:01:01 -0000
@@ -302,15 +302,28 @@ hal_enable_caches(void)
     HAL_DCACHE_INVALIDATE_ALL();
     HAL_ICACHE_INVALIDATE_ALL();
 #endif
 
 #ifdef CYGSEM_HAL_ENABLE_ICACHE_ON_STARTUP
+#ifdef HAL_ICACHE_UNLOCK_ALL
+    HAL_ICACHE_UNLOCK_ALL();
+#endif
     HAL_ICACHE_ENABLE();
 #endif
 
 #ifdef CYGSEM_HAL_ENABLE_DCACHE_ON_STARTUP
+#ifdef HAL_DCACHE_UNLOCK_ALL
+    HAL_DCACHE_UNLOCK_ALL();
+#endif
     HAL_DCACHE_ENABLE();
+#ifdef HAL_DCACHE_WRITE_MODE
+#ifdef CYGSEM_HAL_DCACHE_STARTUP_MODE_COPYBACK
+    HAL_DCACHE_WRITE_MODE(HAL_DCACHE_WRITEBACK_MODE);
+#else
+    HAL_DCACHE_WRITE_MODE(HAL_DCACHE_WRITETHRU_MODE);
+#endif
+#endif
 #endif
 }
 
 //---------------------------------------------------------------------------
 //A jump via a null pointer causes the CPU to end up here.
Index: hal/powerpc/mpc8xx/current/ChangeLog
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/mpc8xx/current/ChangeLog,v
retrieving revision 1.16
diff -u -5 -p -r1.16 ChangeLog
--- hal/powerpc/mpc8xx/current/ChangeLog	27 Jun 2002 20:27:18 -0000	1.16
+++ hal/powerpc/mpc8xx/current/ChangeLog	13 Nov 2002 21:02:16 -0000
@@ -1,5 +1,10 @@
+2002-11-13  Gary Thomas  <gthomas@ecoscentric.com>
+
+	* include/var_cache.h (HAL_DCACHE_WRITE_MODE): Define for support
+	of various modes (copyback/writethru)
+
 2002-06-27  Gary Thomas  <gary@chez-thomas.org>
 
 	* include/var_regs.h: Allow platform to override certain assumptions,
 	e.g. the IMMR base, via <plf_regs.h>.
 
Index: hal/powerpc/mpc8xx/current/include/var_cache.h
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/mpc8xx/current/include/var_cache.h,v
retrieving revision 1.3
diff -u -5 -p -r1.3 var_cache.h
--- hal/powerpc/mpc8xx/current/include/var_cache.h	23 May 2002 23:04:27 -0000	1.3
+++ hal/powerpc/mpc8xx/current/include/var_cache.h	13 Nov 2002 20:40:32 -0000
@@ -146,14 +146,28 @@
 
 // Set the data cache refill burst size
 //#define HAL_DCACHE_BURST_SIZE(_size_)
 
 // Set the data cache write mode
-//#define HAL_DCACHE_WRITE_MODE( _mode_ )
+#define HAL_DCACHE_WRITE_MODE( _mode_ )                 \
+    CYG_MACRO_START                                     \
+    if (_mode_ == HAL_DCACHE_WRITETHRU_MODE) {          \
+        asm volatile ("sync;"                           \
+                  "mtspr %0, %1;"                       \
+                  : : "I" (CYGARC_REG_DC_CST),          \
+                      "r" (CYGARC_REG_DC_CMD_SW));      \
+    }                                                   \
+    if (_mode_ == HAL_DCACHE_WRITEBACK_MODE) {          \
+        asm volatile ("sync;"                           \
+                  "mtspr %0, %1;"                       \
+                  : : "I" (CYGARC_REG_DC_CST),          \
+                      "r" (CYGARC_REG_DC_CMD_CW));      \
+    }                                                   \
+    CYG_MACRO_END
 
-//#define HAL_DCACHE_WRITETHRU_MODE       0
-//#define HAL_DCACHE_WRITEBACK_MODE       1
+#define HAL_DCACHE_WRITETHRU_MODE       0
+#define HAL_DCACHE_WRITEBACK_MODE       1
 

 // Load the contents of the given address range into the data cache 
 // and then lock the cache so that it stays there.  
 


-- 
------------------------------------------------------------
Gary Thomas                  |
eCosCentric, Ltd.            |  
+1 (970) 229-1963            |  eCos & RedBoot experts
gthomas@ecoscentric.com      |
http://www.ecoscentric.com/  |
------------------------------------------------------------


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